Custom ASICs always offer the best performance, power consumption,security and unit cost of any silicon-based solution. Cell-based ASICsprovide the best characteristics because the poly and diffusion layersfor interconnect, and transistors can be sized to optimize speed,density, and power dissipation according to each particular cell'srequirements.
This approach provides for a silicon-efficient design, but isexpensive because it requires a full mask set. Mask costs increasesharply with shrinking process technology or feature size.
Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthydesign time associated with standard cell ASICs puts them out of reachfor many products. In fact, in applications such as MP3 players or cellphones, the technology evolves so rapidly that the next generationproduct must be launched every six months — about half the timerequired to implement a cell-based ASIC.
The pros and cons of gate arrays
Gate array technology uses anarray of identical transistors with a metal interconnect to createlogic functions. Since customization is accomplished through therouting, masks are required for only the metal interconnect and NREcharges are much are in the $100,000 to $150,000 range.
Design turn around is about three months ” one-third the requirementfor cell based ASICs –because most of the silicon processing is done before” the die is”personalized”. Since one set of under-layer silicon masks can servemore than one design, the engineering and mask costs associated withgate arrays tend to be substantially lower than those for cell-basedASICs.
Platform ASICS vs gate arrays
Platform ASICs havefurtherimproved the quick turn-around time and lower non-recurring eniginnering (NRE ) cost of gate arrays by providing apre-designed mix of metal programmable blocks and microprocessor cores,memories, analog blocks, or peripherals. With common IP blocks, such asa UART or serial interface, there is little value to be gained frombuilding from scratch, so these pre-designed and validated cores arere-used, as is in a platform approach.
Many platforms can be defined using a standard product ARM-baseddesign data base. In fact, many of these designs are prototyped usingthe standard product along side an FPGA for initial prototyping. Mostsystems have many elements in common, so a single platform based on anexisting set of masks may be used for multiple ASIC designs. New masksare required only for the unique part of the design, which isimplemented by adding a new metal interconnect with custom logic.
Structured ASIC features
With careful architectural design, structuredASICs can be designed with the right complement of fixedfeatures to satisfy the requirements for a range of products in a givenmarket or a family of evolving products for a particular customer. Thisintelligent re-use of pre-defined elements brings NRE charges down toan even lower level.
The time to market and technical risk are also reduced significantlywith a platform ASIC because the wafer is fabricated by manufacturingonly the metal interconnect layers. This process takes less than halfthe time required for a cell-based ASIC. Since the platform itself hasalready been verified, only the custom logic for the ASIC's”personality” need be.
Given this reduced design complexity, the development and prototypeevaluation times can be substantially reduced with a structured ASIC,especially those using a common ARM-based architecture. Even so, gatearrays are less silicon efficient, resulting in substantially higherunit costs than cell-based ASICs. Gate arrays also tend to have worsespeed and power characteristics.
For example, in a 180 nm process, a standard cell flip-flop consumesroughly half as much area as a D flip flop implemented in a gate array.Cell based ASICs have about twice the gate density and half the unitcost of a gate array implementation (SeeFigure 1, below ).
|Figure1. D-type flip-flop in 180 nm gate array and 180 nm standard cellimplementations.|
Early structured ASICs once were expected to provide lower NREs thanconventional ASICs and lower price points than high priced FPGAs. Thefact is that FPGAs keep getting cheaper and structured ASICs' unitcosts are rarely low enough to offset the relatively high NRE costs andrisks. The re-programmability of FPGAs provides a measure offlexibility that can never be achieved by any ASIC.
As a result, the majority of today's designs are implemented using anoff-the-shelf standard product microcontroller and a low-cost, off-the-shelf FPGA.This MCU-plus-FPGA combination has effectively replaced ASICs in manyapplications.
A microcontroller with the right mix of peripherals implements themost of the application, while the FPGA is used for the “secret sauce”that differentiates the product, such as DSP algorithms or customlogic.
The re-programmability of both the MCU and the FPGA offer nearlyperfect flexibility to meet changing market needs. There are no NREsand time-to-market is just about instantaneous.
FPGAs do have some drawbacks, however. The extra transistorsrequired for programmability bloat FPGA die sizes to two or three timesthat of the non-programmable implementation. Routing and otherconstraints result in very low logic utilization in FPGAs. Only about10% of the 150 gates in a typical FPGA cell will actually be used.
Thus, although FPGA unit costs do decline as volumes increase,prices stall at about 10,000 units. The next stop for cost-reducing adesign is at 100,000 units, where unit volumes can support the NRE ofconventional ASICs (Figure 2, below) .
|Figure2. Unit Prices & Volumes for FPGAs, Standard Cell, Cell-based andMPCF ASICs.|
Those extra transistors that enable FPGA programmability also gobbleup power. FPGA cell sites are large requiring longer wire lengths andthere are a lot of unused transistors within the cells consuming power.
Another less obvious reason is because they require a very uniform,structured clock tree with relatively few independent clocks, and theycan not support significant amounts of clock gating to reduce currentconsumption. For example, a 65nm Virtex 5 consumes over 3 Watts when executing a PCIe with 8 endpoints!
Security is another issue with SRAM-based FPGAs. Proprietaryalgorithms, that can take decades to perfect, are subject to piracybecause the FPGA design resides in external memory.
Even if there is a security bit in the on-chip flash that preventsit from being read, the FPGA netlist must be re-loaded into the FPGAevery time the system boots up, making it vulnerable to theft. Althoughsome FPGAs have some security features, the IP is not nearly as secureas it is when implemented in silicon.
A new approach: metalprogrammablecell fabric
A new technology, called Metal Programmable Cell Fabric (MPCF), makesit possible to develop ARM-based structured ASICs, with routed gatedensities and unit costs that are nearly identical to those of standardcells in the same process.
A metal programmable cell fabric library iscustom designed andcontains over 400 cells. It has an 8 transistor core cell that is only3.2 um high and 2.0 um wide, and it uses 2 layers of metal forinterconnect. Normally, a sea-of-gates design approach gives about 75%transistor utilization in placed cells plus a 70% placement utilizationyielding a design that is just over 50% routable.
Based on these assumptions at 130 nm, the achievable gate densitywould be 156K gates per mm2. However due to its efficient cell routingand additional metal layers available at 130 nm, ASICs using the MPCFare achieving 80 to 90% placement utilization allowing gate densitieson silicon of between 170K and 210K gates/mm2.
Show in Figure 3, below isthe comparison of a MPCF cell implementing a Dflip-flop (DFF) versus astandard cell DFF both in a 130 nm process. Despite the difference inaspect ratios, the two flip-flops consume nearly the identical area.Actually, the standard cell DFF is larger and consumes 1.07 times morearea than the MPCF DFF, which uses two stacked metal programmable corecells.
|Figure3: D-type Flip-flop in 130 nm MPCF and 130 nm Standard Cell|
As one can imagine, given this cell comparison, the routing densityfor the MPCF library is essentially the same as the standard cellrouting density at 130 nm. In fact, routing studies show that there ismore variation in routing density from design to design than fromstandard cell to MPCF.
In addition, the speed performance of the MPCF also appears to benearly equal to that of the standard cells. However as might beexpected, the MPCF cells do consume 10 to 15% more current than thestandard cells in the same process technology.
Metal-programmable cells and standard cells can be placed inseparate regions on the die or freely mixed without any die sizepenalty. In fact, a variant metal programmable cell was created for theMPCF with the same cell height, 3.6um, and aspect ratio as the standardcells to allow these cells to be placed in empty locations within astandard cell region of the die.
These filler cells take-up no extra silicon space and they areinitially programmed as a decoupling capacitor. If an engineeringchange is required, any new logic can be implemented using these metalprogrammable filler cells.
Given this design approach, engineering change orders (ECO's) aremuch easier to route than with the traditional method of using acluster of spare cells because the filler cells are more evenlydistributed and can be made to implement any logic function required.
As a result, more complicated ECO's that affect over 10% of thelogic can be successfully routed whereas a conventional flow usingspare cells can only accommodate ECO's that affect up to 1% of thelogic.
The MPCF can be integrated with a variety of microprocessor cores,most commonly ARM7 and ARM9; DSP cores, digital IP blocks, analogcells, and I/O and package options. The same design tools from Cadence,Mentor Graphics, and Synopsys as are used for standard cell ASIC designcan be used to design with the MPCF.
Since the overall platform cost is lower with MPCF ASICs, multipleand very low-cost derivatives ($30K to $100K) can be developed fortarget specific markets including automotive, embedded displays,military and industrial control systems and utility meters. This isalso an ideal platform methodology for fabless semiconductor companiesthat need to create a new product line (Figure4, below ).
|Figure4. FPGA vs ASIC costs|
Using this technology, fabless semiconductor companies can developcustom ARM-basedplatforms that are prototyped using an off-the-shelfARM microcontroller and an FPGA.
Like any conventional ARM-plus-FPGA design, the prototype design canbe used for production while volumes are low. Once market acceptance isverified, the prototype can then be migrated it to an ARM-based MPCFplatform with quick turn-around, low NREs and with unit costs thatapproach those of standard cell ASICs.
Customers can develop proprietary ARM-based MPCF platforms thatallow their products to efficiently evolve with new functions orfeatures as their markets change. Consider the metrics shown in Figure 5, below .
|Figure5. Block diagram of an ARM-based MPCF SoC|
With an MPCF platform, the customer decides exactly what is in thechip, including the right peripheral set, memories and matching theright gate count for their custom IP. With NREs of as low as $150,000,and unit prices close to those of cell-based devices, an MPCF platformis cost-effective at volumes as low as 25,000 units.
Another important consideration is migration from a standardproduct. MPCF platforms can be modeled after ARM-based standardproducts now available on the market. The ARM-core platform, is alreadyqualified in silicon via the standard product. Not only does thisreduce the risk, but also offers a seamless migration path from thesestandard off-the-shelf ARM products to a cost effective customsolution.
The design used to test the market and garner market share can bedirectly ported to the MPCF-based platform ASIC. Moving the ARM core,AMBA bus and peripherals into a SoC and converting the IP in the FPGAto a cost effective one-chip solution becomes a much easier path. Theeffective end result is the right combination of NRE, unit price andease of use.
Existing, low cost ARM7 and ARM9 hardware development platforms allowsoftware to be co-developed with seamless migration to an MCPF ASIC.Power consumption of an MPCF-based structured ASIC will be very closeto that of a stand-alone MCU without an ASIC – roughly 10mA static foran ARM9-based SOC.
This is two orders of magnitude less than the 1900 mA consumed byand FPGA. Since the logic that was in the FPGA is programmed in themetal fabric of the MPCF-based ASIC, it is immune to software pirating.
There is no need to develop an ASIC-style design methodology becausean MPCF ASIC can be easily migrated directly from standard products.The MPCF platform can retain much of the flexibility of itsFPGA-prototype, while offering unit prices comparable to those ofcell-based ASICs, even at relatively low volumes. As a result, we mayexpect to see renewed growth in the structured ASIC market.
Next in Part 2: Building aMPCF/MCU-based custom SoC
Jay Johnson is ASIC MarketingDirector at AtmelCorp.