# Using dynamic voltage and frequency scaling to conserve system battery power requirements

It is necessary to reduce energy consumption in circuit operations toachieve longer battery life in mobile devices. One new energy reductionscheme is to combine dynamic voltage and frequency scaling with powergating. This article discusses other previously proposed approaches toenergy reduction and introduces the new scheme.

The energy consumed by mobile devices is a combination of switchingenergy and leakage energy. When switching energy is predominant,reducing supply voltage levels is effective in decreasing total powerconsumption because switching energy is proportional to the square ofsupply voltage.

Dynamic voltage and frequency scaling (DVFS), which controls supplyvoltage in accordance with operational frequency requirements, isparticularly effective for this purpose.

**Operational frequency**

In Figure 1 below , the solidblack curve shows energy-consumption dependence on operationalfrequency under DVFS. Here, operational frequency decreasesmonotonically along with decreases in supply voltage.

When operational frequencies are higher than those for the minimumenergy point (MEP), at which the supply voltage is optimal (Vopt),energy consumption decreases along with decreases in operationalfrequency. When operational frequencies are lower than those for theMEP, however, energy consumption increases along with decreases inoperational frequency.

When the supply voltage is close to the threshold voltage of LSItransistors, even slight variations in it can create large variationsin operational frequencies. In such situations, any reduction inswitching energy resulting from a supply voltage decrease will beoutweighed by the increase in leakage energy due to increased operationtime, and total energy will therefore increase.

In this situation, DVFS alone is not enough to reduce energyconsumption. However, a proposed technique that combines DVFS withpower gating – a leakage reduction technique in which a power switchinserted between the power supply and the target circuit turns offduring target-circuit idle times–proves much more effective.

With the combination of DVFS and power gating, when a requiredfrequency is lower than that for the MEP, the target circuit operatesat Vopt and leakage energy is reduced by power gating during idletimes.

Although higher supply voltage results in increased switchingenergy, total energy is reduced by more than that of DVFS alone becauseof the reduction in leakage energy (seered solid curve in Figure1 below, which also shows ablock diagram of the scheme ).

Figure 1: The solid black curve shows energy-consumption dependence on operational frequency under DVFS. |

A MEP monitor determines the Vopt for minimizing energy consumption,and a delay monitor determines the minimum supply voltage valuerequired to meet frequency requirements and outputs a control signal toa regulator, which responds by supplying the appropriate voltage to thetarget circuit.

When a determined supply voltage is lower than Vopt, the MEP monitordisables the control signal, and the supply voltage is maintained atVopt. When the target circuit operates at Vopt, the MEP monitor alsoenables the power-gating controller to control the power switch toreduce leakage energy during idle times.The MEP monitor controls theoverall system for minimizing the energy of operations and is the keycomponent in the scheme.

While energy reduction depends heavily on how accurately Vopt isdetermined, accuracy here is not easy because Vopt depends heavily onthe leakage current, which in turn depends on temperature, supplyvoltage and other factors. A number of different approaches havealready been proposed to deal with this issue.

**Conventional vs. new**

One approach is to determine Vopt on the basis of the measurements ofactual energy consumption in the target circuit at various supplyvoltage levels, and select the voltage with the least energyconsumption. Because the target circuit itself is used as an energymonitor, this scheme is highly accurate with respect to the MEP, butcircuit operations have to be suspended during monitor operations.

Another conventional approach is to use theoretical equations. Forexample, one method reported is based on the fact that delta Eall/delta VDD = 0 at MEP. In this approach, Vopt is expressed as Equation2.

Unfortunately, this approach does not appear to be suitable forcircuit implementation because it includes a parameter n whosedependence on supply voltage is nonlinear. NEC has devised a newapproach for determining Vopt, which consists of simple components andis suitable for circuit implementation.

In contrast to previous methods, this new technique allowssimultaneous monitor operation and circuit operation and has beenproven feasible for implementation. It is based on the fact that deltaEall VDD = 0 at MEP, where Eall is expressed as Equation 1 of Figure 1 above .

Note that (IL1T1-IL2T2)/Delta V is substituted for delta ILT)/deltaVDD the differentiation of the equation. Equation 3 can then be derivedwith an approximation, where Delta V is much smaller than VDD. IL1 andT1 are, respectively, leakage current and critical path delay at VDD,while IL2 and T2 are those at VDD-Delta V. As both leakage current andcritical path delay can be measured with monitors, Equation 3 issuitable for circuit implementation.

On the basis of Equation 3, we can determine Vopt as follows: Itsright side is equal to the voltage of a capacitor initially charged toVDD, then additionally charged for a period of T1 with IL1, anddischarged for a period of T2 with IL2, where the capacitance of thecapacitor is the product of the switching capacitance andswitching-activities of the target circuit. If, for a given VDD, thevoltage of the capacitor is equal to VDD-Delta V, that VDD will be theoptimal voltage for minimizing energy consumption.

Figure2: Shown are the proposed optimal voltage determiner and measurementresults |

**Circuit implementation**

Figure 2 above shows thecircuit for determining Vopt. It is a very simple circuit, consistingof a variable capacitor whose capacitance is alpha x C0; two leakagecurrent generators, each containing a replica of the target circuit;two pulse generators, each containing a critical path replica of thetarget circuit; one comparator; and three switches. IL1 and IL2,respectively, flow from and into each of the two leakage-currentgenerators.

SW1, SW2 and SW3 are turned on to initially charge, additionallycharge and discharge the capacitor, respectively. To turn on SW2 andSW3, the pulse generators produce signals with pulse widths of T1 andT2, respectively.

A test chip was fabricated with 90nm CMOS technology to evaluate theeffectiveness of the circuit, as well as the combination of DVFS withpower gating. The target circuit was a 101-stage ring oscillatorconsisting of two input NAND gates of F.O. = 4.

Figure 2 shows the dependence of energy on supply voltage for thetarget circuit, as well as the points determined with the determinercircuit, where Delta V = 20mV. The curves represent three temperatures(25, 75 and 125 degrees C) under the condition that switching activityis0.1.

The circuit accurately determined optimal voltages within 50mV ofactual voltage values for MEPs under all conditions. Figure 2 alsoshows that at 125°C and where Vopt=0.67V, Vopt operations withpower gating at 40MHz result in an energy reduction of 52.8 percent,more than that achieved with DVFS alone at 5MHz.

*Yoshifumi Ikenaga is with the Device Platforms Group at NEC Corp.'s Research Laboratories*