High-performance MPUs require a low-voltage, high-current power supplywith fast transient response. Thus, interleavedmultiphasesynchronousbuck converters have beenpopular asa voltage regulator module because they allow faster system controllersin small signal conditions, reduce output voltage ripple and decreasecost of I/O capacitors.
However, interleaving phase shift during large and steep loadtransients can negatively affect output voltage. System stability andsmall signal behavior are studied based on AC variables related tooutput power. State variables for the system are total current flowingthrough the equivalent inductor and voltage drop across the outputcapacitor.
A multiphase interleaving system is totally characterized by suchvariables. It is equivalent to a single-phase DC/DC converter where the coilissubstituted by the parallel of all inductors (equivalent inductor ) . Theequivalentswitching frequency is n times the single-phase switching frequency,where n is the number of phases.
This model demonstrates why it's possible to implement a fastercontrol system with much higher gainbandwidth product (GBWP) than a single phase system. Ofcourse,this helps to keep the output voltage stable and well-regulated evenduring load transients.
Unfortunately, recent electrical CPU specifications have raised loadtransient rates to up to 1,200A/microsecond (100A with 50ns), making italmost impossible for the control system to respond in time to suchsteep variations. The result is an increase in the cost of the outputfilter capacitors above all mid-frequency range capacitors such as the22 microFarad multilayer chip capacitors (MLCCs).
Controller architectures used today are typically either trailing edgeor leading-edge (Figure 1 below ).Controllers using the trailing-edge control architecture turn on at thebeginning of every clock cycle.
|Figure1. Controllers using trailing-edge control turn on at the beginning ofevery clock cycle. Controllers using leading-edge architecture turn offat the clock cycle and can respond to transients that occur while it isoff.|
The controller can respond to any transient event that occurs whilethe controller is on. However, it must wait until the next clock cycleto respond if a transient occurs while it is off. Controllers using theleading-edge architecture turn off at the clock cycle and can respondto transients that occur while it is off.
However, it must wait for the next clock cycle to respond if thetransient occurs while it is turned on. In both architectures, a latchtypically placed at the output of the pulse-width modulation (PWM)comparator creates a onecycle delay when responding to a transientevent.
|Figure2. The dual-edge modulator is not constrained by clock cycles whendetermining when to turn on or off.|
The dual-edge modulator is not constrained by clock cycles whendetermining when to turn on or off (Figure2 above ). The signal to turn on is determined by the errorsignal.
Similarly, the error signal tells the controller when to turn off.This architecture, coupled with fast output feedback, allows all phasesto simultaneously respond to a transient event. While the basicdual-edge modulator enables system improvements, it is also importantto address other pieces of the architecture that introduce delays inthe system response and hinder the ideal instantaneous response.
We can consider action delay (AD) as the time a controller takesbetween realizing a load transient occurrence and commanding allhighside power MOSFETs to turn on.
|Figure3. The remote buffer introduces a delay Trb because it is along thefeedback path.|
Remote sense is used to sense in a full differential way the voltageacross the CPU. It is implemented with an op amp that introduces adelay Trb that is 1/GBWPrb (Trb = 100ns), where GBWPrb is about 10MHz.The remote-sense ampli- fier must be moved away from the feedback path.This can be done by sensing only the remote core ground, thus losinghighfrequency CMRR.
Figure 3 above showstraditional remote buffer connection. The remote buffer introduces adelay Trb because it is along the feedback path.
In Figure 4 below, theremote sense is implemented outside the feedback path with Trb = 0.Dual-edge implementations that use latches throttle the system responseand limit the benefits of pure dual-edge architecture.
|Figure4. The remote sense is implemented outside the feedback path with Trb =0.|
To achieve the full benefits of dual-edge architecture, the clocksand latches must be eliminated from the system. However, cost-drivensolutions are dominated by controllers that embed power MOSFET drivers,which produce noise at every switching edge, reducing noise immunity ofthe analog front-end with high risk of jitter conditions.
There are several methods to limit substrate noise, such as usingaccurate IC design and noise-insulated silicon components. Two of thesemethods have a large PWM ramp and latched PWM pulses.
Latched dual-edge PWM has great noise immunity characteristics, butit produces a long AD Ta proportional to the switching period. It alsodepends on the instance when a load transient occurs.
In latched dual-edge PWM, the worst AD is given when the loadtransient happens when lowside power MOSFETs turn on (Figure 5 below ). An AD of about T/2is possible, where T is the switching period.
|Figure5. In latched dual-edge PWM, the worst action delay is given when theload transient happens as lowside power MOSFETs turn on.|
In Figure 5 above , you cansee that the dual-edge modulator without latch greatly improves the ADcanceling Ta. The error amplifier local loop must be pulled away fromthe steep output voltage drop when a load transient occurs. In thisway, the control loop can fly over the PWM ramps, forcing all PWMpulses at “1” to turn on highside power MOSFETs at the same time.
It is required that the control voltage (Comp) be saturated. Toproduce the error amplifier saturation, a capacitor Cp is inserted intothe feedback network, as shown in Figure6 below .
|Figure6. To produce error amplifier saturation, a capacitor Cp is insertedinto the feedback network.|
Cp gives a derivative component to Comp. Big Cp capacitor makes thesaturation of Comp faster and easier above PWM ramps, but it makes thesystem unstable or it may produce jitter, so enlarging output voltageripple requires more output capacitors.
The system is stable if Cp is small, but there is the risk that Compmay not rise high enough above the PWM ramp.
The time needed to push the Comp above the PWM ramp depends on thePWM ramp's height and the error amplifier's slew rate and GBWP. Slewrate is usually 10V/microsecond, and the PWM ramp is 2V. We have Tsr =200ns delay from slew rate. The slew rate and GBWP are usually verydifficult to guarantee in a datasheet, because they can spread verylargely.
|Figure7. An increase of Cp creates jitter – it increases output voltageripple, thus creating system instability.|
Such spread makes this part of AD unpredictable. Cp value must bechosen considering that even in the worst slew rate condition (even notknown), the Comp can rise above the PWM ramp.
In Figure 7 above , anincrease of Cp creates jitter – it increases output voltage ripple,thus creating system instability. The steady-state condition isrecovered after much time has passed since the load transient.
There is also a contradiction about the Cp choice – it should bechosen taking into account that even in worst slew-rate condition, theComp voltage can rise above PWM ramp, but the Cp value also sets theamount of energy transferred after the load transient.
The overestimate of Cp brings too much energy to the output, thusproducing a large voltage ring-back and an increase in recovery timefor the steady state, as shown by the simulations in Figure 7 above . We will show that anew class of nonlinear control response will solve this issue,canceling delay Tsr and getting a large improvement of the box-shapedcore voltage response.
|Figure8. Load transient boost solves all action delay contributions – Trb,Ta, Tsr and T1+T2.|
Power drivers are the hard transducers of controller decisions. Itis crucial that power drivers run the command with minimum delay. Thisdelay is the sum of time T1 between the turning off of lowside powerMOSFETs and turning on of high side power MOSFETs and the time T2needed to transfer the logic command to the driver itself.
Controllers with embedded drivers usually minimize this delaybecause they do not have T2. This delay comes from the fairly low speedof digital buffers inside the controller, and the high wire capacitancebetween controller and external driver.
The digital buffer of a commercial controller normally has asaturated driving resistance of about 1k ohm, while the trace wire ofabout 5 inches shows a capacitance of about 100pF, thus we can concludethat T2~ 100pF x 1k? = 100ns.
|Table1. Delay T1 is the sum of driver internal delay, and the Tfall lowsideand Trise highside. T2 delay can be 100ns and T1 can be 100ns as well.|
Delay T1 is the sum of driver internal delay, and the Tfall lowsideand Trise highside. T2 delay can be 100ns and T1can be 100ns as well.The most significant values are listed in Table 1 above . The AD has severalcontributions – Trb, Ta, Tsr and T1+T2.
Solving AD contributions
Load transient boost (LTB) solves all AD contributions and cancels Tsr (Figure 8 above ). sensor, a circuitthat gives a glitch when the dV/dt exceeds an internal threshold. Thesensibility of the circuit can be set by changing the external networkat the LTB pin. The sensor recognizes both applied and released loadtransient.
When a load transient occurs (applied load), a voltage (red) at theoutput of load apply PWM ramp is set to the lower basement of dual-edgePWM ramps. From that value, a ramp is initiated with a slope m.
|Figure9. Each load apply/release PWM ramp is then compared to Comp thatproduces a proper PWM pulse, whose length represents the correct amountof energy needed by the system.|
When the load is released, a voltage (blue) at the output of loadrelease PWM ramp is set to the upper basement of dual-edge PWM ramps.From that value, a ramp is initiated with a slope -m. Each loadapply/release PWM ramp is then compared to Comp that produces a properPWM pulse, whose length represents the correct amount of energy neededby the system (Figure 9 above ).
As a consequence, the error amplifier will continue to work in”small signal” condition. For load release, the pulse will turn off allthe power MOSFETs, particularly the lowside power MOSFETs. This willimprove the output voltage response. For applied load, the “or”operation is used on the PWMBOOST pulse with each PWM pulse for everyphase.
The “or” operation cancels the interleaving phase shift andtransfers the correct amount of energy commanded by the erroramplifier. The LTB brake is a digital filter that allows the closestinterleaved PWM pulse to be skipped to PWMBOOST. This filter improvesthe output voltage response that looks like a box waveform.
The AD related to the LTB technology is a few nanoseconds – itacts directly in a digital way, resetting the interleaved phase shift.The delay is caused mainly by the sensor comparator (about 10ns).
LTB technology reduces Tsr from 100ns to 10ns. Above all, it makesthe system insensitive to a parameter spread that is not guaranteed. Italso makes the system more “linear.” The energy that LTB transfers iscommanded directly by an error amplifier that continues to work as anop amp and not as a comparator pulled away by Cp capacitor.
When all highside power MOSFETs are turned on to increase theinductors' current, the whole charge is brought to sustain the outputvoltage only in AD time. This means that only MLCCs (usually 90percent) can bring up the output voltage because the total MLCCs havean equivalent series resistance (ESR) much less than the total bulkcapacitors. Such that 15 x 10mF MLCC have a total ESR of 0.16milliohms, while 4 x 560µF bulk have a total ESR of 1.5miliohms.The ratio is 1:10. Hence, 90 percent of the needed charge is deliveredby MLCC.
From AD, it is possible to calculate how many MLCCs are necessary tokeep the output voltage within a given drop delta Vout after a loadtransient delta Io with a time length To. After AD, the inductorcurrents grow up in TL, where:
From a geometrical calculation, we have:
MLCC sustains 90 percent of this charge, while 10 percent is givenby bulk capacitors. Thus, we get:
The AD, thus the number of MLCCs, is very important because it isdirectly related to cost.
Simulations, resultsThe simulation results are based on the following BOM andspecifications:
The simulation results show how the interleaved phase shift iscancelled. When the interleaved phase shift is zeroed, the outputvoltage is sustained by MLCC and above all, by 22 microFarad MLCCs. Toget rid of any ring back or excess of transferred energy, the LTB brakemechanism reduces the current flowing into one of the three inductors (Figure 10, below) .
|Figure10. To get rid of any ring back or excess of transferred energy, theLTB brake mechanism reduces the current flowing into one of the threeinductors. At load release, the LTB pulse turns off all power MOSFETs.|
So, the output voltage features a real output impedance (boxwaveform). The slight undershoot after 4-5 microseconds is the timeneededfor the control loop to recover the steady-state condition. It isrelated to both the total GBWP of the system and current sharing loopgain. At this slow frequency, the system is also sensitive to thenumber of bulk capacitors.
If we use the equations with the electrical specifications reportedpreviously, we have:
This equivalent capacitor corresponds to 15 x 10 microFarad and 3 x22 microFarad.
At load release, the LTB pulse turns off all power MOSFETs. Thisfeature reduces the extra charge of output bulk capacitors, because theslope of inductor currents are greatly increased from Vo/L to (Vo +Vd)/L where Vd is the voltage drop of the body drain diode of lowsidepower MOSFETs.
|Figure11. The experimental results are related to the same BOM andspecifications of the simulated results.|
This feature also avoids the negative current flows into inductors,thus canceling negative ring-back of the output voltage.
The experimental measures were collected using the STML6713A, with a remote-senseout-of-feedback path, asynchronous dual-edge modulator, LTB technologyand embedded drivers. The device can be used with two or threeinterleaved phases and is suitable for Intel VR10.x, Intel VR11 and AMDK8-F processors.
The experimental results are related to the same bill of materials(BOM) andspecifications of the simulated results (Figure 11 above ).
The small ring-back comes from not perfectly modeledmotherboardparasitics. The output voltage spike is higher than the simulation. Theresponse time, which is time needed to recover steady-state condition,for applied load and released load are the same for simulation andexperimental measures. The ADiseffectively around 100 ns. It is also possible to observe the result ofLTB Brake – it clears the phase-switching activity to reduce thering-back of the output voltage.
Osvaldo Zambetti is SeniorDesigner and Alessandro Zafarana is design manager in the industrialand power conversion division at STMicroelectronics.