Using LVDS to compensate for impedance discontinuities in a digital video router design -

Using LVDS to compensate for impedance discontinuities in a digital video router design


Data signal paths become transmission lines at data ratesof 400Mbps to 1.5Gbps. At these speeds, the signal-path model mustinclude thereactive parasiticcomponents in the cable or backplane.

It is not just the data rate itself – fast edge rates contain evenhigher frequency energy that react worse in distributed impedanceenvironments. Ignoring parasitic impedances and impedancediscontinuities above 200 Mbps will add noise in the transmission line,thus causing data bit errors.

HD video router
Consider a basic high-definition (HD) digital video router as anexample of this challenge. HD video routers manage multiple HD sourcestreams to distribute in broadcast, studio or production videofacilities.

HD video channels operate from 270Mbps to 1.485Gbps, demandingcareful layout and consistent design practices. This is to ensure thatthe switching router system does not degrade the integrity of the videodata.

Figure1: A common backplane connects the signals from the input card to theswitch card for output to the channel.

In Figure 1 above , an adaptive equalizer (EQ) receivesthe HD signal directly from the BNC connector. A common backplaneconnects the signals from the input card to the switch card for outputto the desired destination channel.

The signals travel point-to-point from the EQ across the printed circuit board (PCB)approximately 8 inches to the backplane connector. It then travelsacross  about 3 to 15 inches of backplane depending on the slotused to a second connector.

It moves across another 8 inches of PCB to the inputs of thecrosspointswitch device. A re-clocker/cable driver connects directly tothe outputs of the crosspoint switch to drive the signals acrosscables.

These HD video router systems are modular and may have 8 to 1,000I/O channels. Signal density can thus be very high. The common FR4circuit board materials are a consistent impedance environment, butthe distributed parasitic impedances will have a negative effect onsignal quality.

Figure2: All the interconnections between the components can cause impedancemismatches from the characteristic impedance Z0, which will also affectsignal quality.

Most affected are the fast edge rates resulting from the manyfrequency components operating higher than the fundamental data rate,which in turn cause signal losses and sluggish transition times.

Moreover, all the interconnections between the components, such asthe BNC connectors, ICs, viasbetween board layers or the connec tors between boards, can causeimpedance mismatches from the characteristic impedance Z0, which willalso affect signal quality (Figure 2above) . The dense backplane connectors inductively load thesignal path, while vias in the PCB load the signal path.

Signal reflections will occur at any location along a transmissionpath where a change in impedance exists. These reflections andparasitic impedances will cause loss ofsignal amplitude ,ringing , rise-time degradation and EMI.

In this example system, there can be up to 31inches of FR4 from theEQ outputs to the input of the crosspoint switch with several impedancediscontinuities along the way.

Figure3: The resulting eye pattern shows the loss of amplitude, excessivejitter and rise/fall-time degradation.

If the speed of the incident edge is 175-200 ps/inch down this pathand the data rate is 1.485Gbps (half-wavelength = 343ps), there can beas many as 18 transitional edges on the path at any given time.Reflections caused by the incident edge at impedance mismatches willaffect all the edges present on the signal path.

Reflections from edges 1 to 17 will greatly distort edge number 18by the time it arrives at the end of the signal path. The resulting eyepattern shows the loss of amplitude, excessive jitter and rise/falltime degradation (Figure 3 above ).

Improving quality
A possible solution to this challenge is to use higher-qualityconnectors between the daughter cards and the backplane. This willminimize the discontinuities of the connectors.

Better via design will further flatten the time-domain reflectometermeasurement plots so that the apparent impedance over the length of thesignal path stays much closer to Z0.

Figure4: To overcome impedance discontinuities, place a buffer at the edge ofthe daughter card to drive the connector and backplane, and a secondbuffer on the switch card to receive the signals

A more cost-effective solution is to use a simple LVDSbuffer, such as the DS90LV004, to drive and receive thesignal across the backplane. This effectively breaks the transmissionpath into smaller segments to mask the impedance mismatch and diminishsignal attenuation.

Place a buffer at the edge of the daughter card to drive theconnector and backplane, and a second buffer on the switch card toreceive the signals (Figure 4 above ).

Re-drive them to the input of the crosspoint switch to effectivelyhide the impedance discontinuities between the two buffers (Figure 5 below ). Proper terminationsalso ensure that the receiver absorbs all the energy in the line andnone reflects back to the source.

Figure5: To effectively hide the impedance discontinuities between the twobuffers, re-drive buffers to the input of the crosspoint switch.

In addition, the buffers typically offer additional signal-qualityenhancements to improve the original signal. For example, buffersfeaturing input equalization will remove the deterministic jitter fromthe media losses before delivery across the backplane.

Output pre-emphasis can boost the amplitude of the signal, furtheropening the eye pattern at the crosspoint inputs or receiver. High ESDratings on the buffer I/O protect the other components on the daughtercards from ESD events elsewhere on the backplane.

Brian Stearns is PrincipalTechnical Marketing Engineer at NationalSemiconductor

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