Using magnetoresistive memory devices in embedded systems designs - Embedded.com

Using magnetoresistive memory devices in embedded systems designs

The core operating structure of a magnetoresistive RAM (MRAM) device isa magnetic tunnel junction (MTJ).

The bit state is stored as the relative magnetization orientation oftwo magnetic layers in direct contact with a tunnel barrier, with anantiparallel orientation (high state) having a higher junctionresistance than a parallel orientation (low state). The bit state isread out by passing a current through the junction and comparing thejunction voltage to a known reference.

Freescale's MR2A16ATS35C 4Mbit MRAM is manufactured in a 0.18micrometer six-metal process with a 256K x 16bit configuration, runs ona 3.3V supply and is available in a 44-pin TSOP type-II package.

Such an unusual part always catches our attention, so we couldn'tresist looking inside to see how Freescale put it all together.

Figure1. The contacts seen at the center of the upper plate go to a commontop electrode, and those at the top edge of each lower plate go down toan isolation (select) transistor in the substrate.

Operation principle
The Freescale MRAM cell has multilayer MTJs placed diagonally betweentwo high-current write line conductors, which are formed in metal 4 andmetal 5, and arranged at right angles to each other. The chip has beendelayered to expose an array of MTJ structures, showing the smaller topplates overlying the larger bottom plates (Figure 1, above ).

We can just see the lower write lines under the array of junctionplates. The contacts seen at the center of the upper plate go to acommon top electrode, and those at the top edge of each lower plate godown to an isolation (select) transistor in the substrate.

Figure2. The device uses magnetoresistive tunneling across an insulatingtunnel barrier, sandwiched between two SAF layers, with the top SAFlayer a “free” layer and the bottom SAF a “fixed” reference layer.

Figure 2 above illustratesthe principle of operation of an MRAM cell. The device usesmagnetoresistive tunneling across an insulating tunnel barrier,sandwiched between two synthetic antiferromagnetic (SAF) layers. Thetop SAF layer is “free” (i.e. its magnetic moment can be programmed),and the bottom SAF is a “fixed” (not programmable) reference layer.

Figure 3 below shows thelower M4 write lines in cross-section and a linear section of an upperM5 write line, with the MTJ structure in between (There are some voidsfrom sample preparation in this image.).

Figure3. Shown is the lower M4 write lines in cross-section and a linearsection of an upper M5 write line, with the magnetic tunnel junctionstructure in between.

Multiple layer structure
Both the top and bottom SAF layers are actually three sublayers, twoferromagnetic layers separated by a non-magnetic spacer; the freeferromagnetic sublayers use a magnetically programmable material withalmost balanced magnetic moments.

This allows the magnetic moments to rotate like a pair of linked”clock hands” when the magnetic field is applied. The tunnel barrier isaluminum oxide. The transmission electron microscopy image in Figure 4 below shows the multiplelayer structure.

Figure4. Both the top and bottom SAF layers are actually three sublayers, twoferromagnetic layers separated by a non-magnetic spacer; the freeferromagnetic sublayers use a magnetically programmable material withalmost balanced magnetic moments.

The use of this type of structure – in its diagonal orientation -allows the magnetic moments to be toggled 180° using the sametwo-phase pulse sequence regardless of state, using both write lines.This requires a pre-read to see if a write sequence is needed, butprotects the datum state from a single pulse on either one of the writelines (Figure 5 below ).

The write lines themselves have some interesting structural quirksto optimize the magnetic coupling to the MTJ. Not the least interestingis that they are made of copper.

Figure5. The write lines themselves have some interesting structural quirksto optimize the magnetic coupling to the MTJ.

Meanwhile, the bond pads and lower metal layers are the conventionalaluminum consistent with the 0.18µm process. This is presumed toallow higher current density, to give a higher magnetic field and keepthe cell pitch down.

The inlaid damascene structure also aids the use of magneticallypermeable cladding layers, which concentrate the magnetic fields -Freescale claimed double the magnetic flux when these layers wereadded.

The cladding in the bottom write line focuses the magnetic fieldupwards into the tunnel junction. This is elegantly achieved by addinga nickel-iron (NiFe) layer to the barrier layer structure of thedamascene line (Figure 6, below ).

Figure6. The NiFe is laid down as an outer barrier layer, and then the usualTa-based barrier before filling the trench with copper.

The NiFe is laid down as an outer barrier layer, and then the usualtantalum (Ta)-based barrier before filling the trench with copper.

The upper write line is more difficult to make. This is because tofocus the field down on to the MTJ, we need to have the cladding on thetop and sides of the line (Figure 2).

Figure 7 below illustrateshow Freescale achieved this: they put down a Ta barrier layer followedby the NiFe layer on the bottom and sidewalls of the trench. Then, theNiFe is sputtered away from the trench bottom and another Ta barrierlayer is deposited.

The trench is filled with copper and planarized as usual, andnitride and oxide metal cap layers are deposited. These are masked andetched to expose the top of the M5 copper in the memory array. A secondset of NiFe and Ta layers are deposited, and then polished back toremove the excess and isolate the lines, leaving “wings” at each lineedge.

Figure7. Freescale put down a Ta barrier layer followed by the NiFe layer onthe bottom and sidewalls of the trench. Then, the NiFe is sputteredaway from the trench bottom and another Ta barrier layer is deposited.

It's a relatively complex process, but it achieves the desired end.That covers the basics of the MTJ. With the lower metal levels beingaluminum, and M4 and M5 copper, the device is one of the few parts witha true hybrid metallization structure, as distinct from the coppermetal with Al bond pads in most 130nm and smaller parts.

This is a clue to the fab history of the part. When we looked at thefront-end structure (i.e. transistors + M1 ” M3), it looked very muchlike Taiwan Semiconductor Manufacturing Co. Ltd's 0.18 micrometerprocess that we've seen in other devices. Discreet inquiry revealedthat the front-end was indeed outsourced to TSMC, and then the waferswere shipped back to Chandler to add the MRAM structure.

Embedded use
According to Freescale, the major advantage of this MRAM technology isthat it is a back-end addition to conventional CMOS and is thussuitable for embedded use. This fab sequence would seem to be a cleardemonstration of that statement.

As a manufacturing strategy, I think it also makes a lot of sense.It keeps the wafer cost down to foundry levels and also allows tighterinventory control for a speculative product launch – keep a stock offront-end wafers and only add the back-end as needed by order volume.

The MRAM cell size of 1.3 square micrometers compares well with SRAMcell sizes of that generation. One of the target markets is battery-backed SRAM storage used for applications such as data logging, and thedevice is packaged with an SRAM-compatible pinout.

With this part, Freescale has come up with a technology that couldhave some disadvantages in terms of price and performance. However, asa solution requiring zero power to store data, it will find someapplications in the automotive, aerospace and similar markets.

Dick James is Senior TechnologyAdvisor at Chipworks Inc. To read a PDF version of this story, go to “ MRAMputs new spin on process, fab strategy.” 

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