This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
Traditionally, analog IC designers boosted supply voltages andoperating current to maximize device speed of operation and dynamicrange. But that is no longer possible in today's energy- consciousworld.
Maximum frequency of operation, useable bandwidth, noiseperformance and dynamic range must continually improve while powerconsumption remains flat or decreases. In short, the industry isdemanding components with better performance-to-power ratios.
National Semiconductor's PowerWise products are developed usingnovel architectures on state of the art manufacturing processesresulting in industry leading performance at exceptionally low powerconsumption.
Using the reference design platform shown in Figure 1 below, this articledemonstrates how a complete analog system can be developed usingenergy-efficient ADCs, fully differential amplifiers and clockconditioning circuits.
|Figure1: This reference design platform shows a complete analog systemdeveloped using ADCs, fully differential amplifiers and clockconditioning circuits.|
Tailored to fit
A given process technology designed for ADC development will notnecessarily be suitable for developing high frequency low noiseamplifiers. In fact, normally companies use several different processtechnologies, CMOS, BiCMOS, SiGe etc. depending on the desiredcomponent parameters. Exceptional circuit design alone is inadequatewithout exceptional process technologies.
National's Advanced Process Technology Development group developshighly characterized and modeled, manufacturable and reliable,innovative and differentiated process technologies.
Special transistors are engineered in-house on several processtechnologies to achieve optimal analog performance at low powerconsumption. National uses pure CMOS technology for the design of manyof it latest ADCs. CMOS is ubiquitous today because CMOS logic gatesdissipate no static power yet have high drive current and speed.
Considering ADCs contain a high percentage of digital circuits,realizing the circuit design on pure CMOS technology results in lowerpower consumption compared to a chip designed, for example, on a BiCMOSprocess. Digital CMOS gates consume no current in DC mode.
Digital bipolar gates on the other hand consume current even in DCmode as bias currents are required to maintain performance parameters.The result is higher current consumption for the digital portion of thechip leading to higher total power consumption.
National has also specially developed processes such as VIP10 foramplifier IC design. VIP10 is a high-speed, dielectrically isolated,complementary bipolar IC process that utilizes deep trench technologyon a bonded wafer for complete dielectric isolation and optimalhigh-speed amplifier performance.
Trench technology with bonded wafers helps minimize parasiticcapacitance for optimal power-to-bandwidth performance, lowerdistortion and decreased die size. Complementary bipolar transistordesigns, by using high-performance NPN and PNP transistors, can offerthe best combinations of features required in today's high speedamplifiers: high bandwidth, low power consumption, low supply voltages,large output swing, high output current and low distortion.
The most common AC figure of merit for a bipolar transistor is thetransition frequency (FT) which is the frequency at which the commonemitter current gain decreases to unity. The FT of the VIP10 NPN andPNP at Vce=5V are 9GHz and 8GHz respectively, about 50 percent higherthan on competitive processes.
The transistor FT being high means that its emitter-base diffusioncapacitance will be low for a given operating point. With VIP10transistors, National can design amplifiers either with bandwidthsexceeding 1GHz or with bandwidths in the 100MHz range with very lowpower consumption.
This is because the internal stages will have low phase shifts evenat very low operating currents, since both diffusion and parasiticcapacitances have been greatly reduced. FT can dramatically decrease atlower voltages on some bipolar process. But FT's on VIP10 remain highat Vce=1V: 7GHz for the NPN and 5GHz for the PNP. Equation 1 below shows how the transition frequency of a bipolar transistor can becalculated.
Here k is Boltzmann's constant, T is absolute temperature, Cte is the emitter capacitance, q is the unit charge of an electron, IC is the collector current, WB is the base width, uB is the electronmobility, rcs is the collector resistance, Ccb is thecollector capacitance, Xs is the width of collector spacecharge region, and vx is the saturation speed of the collector spacecharge region.
We have seen above that best circuit design practices, patentedarchitectures and the latest process technology enable IC designers toengineer industry- leading technology. Such technology empowers systemdevelopers to differentiate their products in highly competitivemarkets.
To gain a further edge over their competition system architectsdemand access to further industry developments. Innovations such asNational's PowerWise technology allow DSP or FPGA power consumption indigital processors to be reduced by up to 70 percent. PowerWise usestechniques such as adaptive voltage scaling (AVS) and threshold scalingto automatically minimize active and leakage power in digital logic ICswith minimal system overhead.
PowerWise technology is unique in the industry in that it is theonly advanced system-level energy management solution available to allIC developers as comprehensive and well documented intellectualproperty packages.
The use of simple standard hardware interfaces and National'scollaboration with industry leaders such as ARM, TSMC, UMC and Synopsysensures that this technology can be used on any CMOS process, withstandard design tools and flows, and can be integrated with any OS orapplication yet resulting in exceptional energy efficiency.
Build analog systems
Reference designs are important in providing engineers a template forgood design practices especially when looking to increase performancewithout increasing power consumption.
Much of the difficult design issues such as proper componentselection and placement, layout and routing are provided in thesereference designs. Building on the knowledge gained from helpingcustomers create high-performance analog systems, National provides alibrary of reference designs that illustrate best system performance.
An example is the latest addition to this library – theADC14DS105KARB Reference Design which uses the new LMH6552 1.5GHzdifferential driver from the PowerWise family as part of the signalchain. This component in combination with the High-Speed ADC14DS105data converter and timing solutions provide a great starting place forengineers involved in designing instrumentation.
Reference design board
The ADC14DS105KARB is a near zero IF receiver reference design boardthat utilizes the following components:
* Two LMH6552 1.5GHz bandwidth differential current feedbackamplifiers;
* ADC14DS105 14bit, 1GHz, Dual 105MSps ADC with serial LVDS outputs;
* LMK02000 low-jitter precision clock conditioner with an integratedPLL that provides 128fs jitter over an integration bandwidth of 100Hzto 20MHz;
* Several energy-efficient power management ICs.
|Figure2: The ADC14DS105KARB is a low IF receiver subsystem reference designboard that enables immediate evaluation of a quadrature directconversion.|
The ADC14DS105KARB is a low IF receiver subsystem reference designboard (Figure 2 above ) thatutilizes a pair of LMH6552 differential drivers and a dual ADC toenable immediate evaluation of a quadrature direct conversion ornear-zero IF receiver for signal frequencies from DC to 40MHz.
This receiver architecture is commonly used in WiMAX and WCDMAreceiver systems. The 1Hz input bandwidth of the ADC and the 1.5GHzdifferential amplifier gain stage enable a large SNR of 73.3dB fullscale (dBFS) and spurious free dynamic range (SFDR) greater than 85dBFSfor input signals up to 40MHz.
In addition to the LMH6552, the board includes the new ADC14DS105dual 14bit, 105MSps low-distortion, low-noise ADC with serialized LVDSoutputs; LMK02000 low-jitter clock conditioner; as well as severalenergy efficient power management ICs.
The LMH6552 is a high-performance fully differential amplifierdesigned to provide the exceptional signal fidelity and widelarge-signal bandwidth necessary for driving 14bit high-speed dataacquisition systems.
Using a proprietary differential current mode input stagearchitecture; the LMH6552 allows operation at gains greater than unitywithout sacrificing response flatness, bandwidth, harmonic distortion,or output noise performance.
With external gain set resistors and integrated common modefeedback, the LMH6552 can be configured as either a differential inputto differential output or single ended input to differential outputgain block. The LMH6552 can be AC- or DC-coupled at the input thatmakes it suitable for a wide range of applications includingcommunication systems and high-speed oscilloscope front ends.
The current feedback topology of the LMH6552 offers gain andbandwidth independence with exceptional gain flatness and noiseperformance, even at high values of gain, simply with the appropriatechoice of the feedback resistors (RF1, RF2). In most of theapplications RF1 is set equal to RF2, so the gain is set by the ratioRF /RG.
The LMH6512 datasheet suggests the optimum value of feedbackresistors for various gains. An excessively large or small RF willcompromise stability. Within reason, the feedback resistor can be usedto adjust the frequency response.
|Figure3: The basic current feedback topology shown is a single-stageamplifier.|
One hidden advantage of current feedback amplifiers is that theyusually require fewer internal gain stages than their voltage feedbackcounterparts. Often a current feedback amplifier consists of merely aninput buffer, one gain stage and an output buffer. Having fewer stagesmeans less delay through the open-loop circuit. This translates intohigher bandwidth for the same power!
The basic current feedback topology in Figure 3 above is a single stageamplifier. The only high impedance node in the circuit is at the inputto the output buffer. Voltage feedback amplifiers usually require twoor more stages for sufficient loop-gain. These additional stages adddelay and yield lower stable bandwidths.
|Figure4: The reference board configuration for the amplifiers is shown. TheLMH6552 is configured for the single-ended-to-differential modeconversion.|
Figure 4 above illustratesthe reference board configuration for the amplifiers. The inputs are 50ohm , DC-coupled. The LMH6552 is con- figured for thesingle-ended-to-differential mode conversion.
The VCOM output of the ADC14DS105 is used as the common mode inputto the amplifier. Each ampli- fier is configured for 6dB of gain, sothe maximum input signal level is 1Vp-p, producing 2Vp-p at the outputof the amplifier.
<>It is recommended that the amplifiers be powered by dual supplyrails(5VDC), but the board can also be configured to operate in singlesupply mode by installing jumpers at VCCAA- and VCCAB-.
To obtain the best SFDR, a low noise signal generator is recommendedto drive the signal inputs of the evaluation board. The output of thesignal generator should be bandpass filtered to suppress any harmonicdistortion produced by the signal generator and to allow accuratemeasurement of the noise and distortion performance.
The 43MHz 5th order low pass filter following the LMH6552 willfurther improve the noise performance of the ADC by filtering thebroadband noise of the signal generator. The filter output is sampledby the ADC.
The ADC14DS105 is the world's first 14bit high-speed, 1GHz fullpower bandwidth, DUAL ADC with serialised LVDS outputs. The serialisedLVDS outputs greatly simplify board layout by significantly reducingthe number of traces that have to be routed across or between PCBs.
The ADC clock used to sample the analog inputs is generated using avoltage-controlled crystal oscillator (VCXO) controlled by the LMK02000precision clock conditioner. The LMK02000 gives the user an ultralownoise PLL paired with a clock distribution section that provides fivelow-voltage positive emitter coupled logic (LVPECL) outputs and threeLVDS outputs (all differential).
|Figure5: The phase noise performance of the clock as measured at CLKout4 ofthe LMK02000 is shown.|
Each clock output channel on the LMK02000 contains a divider blockand delay adjustment clock. The LMK02000 is typically paired with a lowjitter VCXO, in this case the Crystek model CVHD-950X- 100.0, whichprovides a singleended CMOS clock driving the ADC clock input.
The LMK02000 PLL locks this VCXO to a 25MHz reference oscillator(Connor- Winfield model CWX823). The PLL counters, phase detector andcharge pump of the LMK02000 are programmed using the PICmicrocontroller board as discussed in users guide.
The LMK02000 achieves 128fs RMS jitter (integrated from 100Hz to20MHz). Figure 5 above illustrates the phase noise performance of the clock, measured atCLKout4 of the LMK02000. The single-ended clock signal from the VCXO isapplied to the CLK input on the ADC14DS105.
|Figure6: Typical SFDR and SNR performance against input frequency is shown.|
The LMK02000X precision clock conditioners combine the functions ofjitter cleaning/reconditioning, multiplication, and distribution of areference clock. The devices integrate a high-performance Integer-NPLL, a partially integrated loop filter, three LVDS, and five LVPECLclock output distribution blocks.
The combined channel response of the differential amplifier,bandpass filter and ADC is shown in Figure6 above . Note the excellent dynamic performance and matchingbetween channels.
Paul McCormack is Senior ProductApplications Engineer at National Semiconductor Corp.