Since LCDs swaggered into the TV market, demands for higher resolution,bigger panel size and deeper color have grown rapidly. All these callfor a higher data transmission frequency. However, obtaining highertransmission frequency should not compromise the reliability of thedata link.
There is a need for a robust and reliable interface solution totransmit through less data lines working at higher frequency. Thepoint-to-point interface architecture known as Point-to-Point DifferentialSignaling (PPDS' )ensures reliable data transmission to the column driver (CD) from thetiming controller (T-con) through fewer data lines compared with thetraditional multidrop architecture.
At STMicroelectronics, a design team is currently developing ICs totransmit reliable data through only one pair of lanes for full highdefinition (FHD) /120Hz application.
Characteristics of PPDS'
PPDS' uses a protocol that is different from other interfaces. As thisprotocol carries information through data lines, there is no need foroption pins for setup or additional lines.
|Figure1: PPDS' has several benefits, as shown.|
Figure 1 above shows thebenefits of applying PPDS'. As data output pins and other control linesare reduced, the T-con becomes smaller. Separate termination resistorsfor data are not necessary because there are internal terminationresistors in each CD. A thin PCB design is possible due to fewer datalines and less gamma reference voltages.
Moreover, data transmission characteristics improve because thesnaked clock doesn't overlap lines in the PCB design. The eliminationof vias greatly reduces the EMI. Even better, chip sizebecomes smaller with the use of cyclic DACs.
|Figure2: A PPDS' system to realize 10bit colors is shown.|
PPDS for 10bit colors. A PPDS'system to realize 10bit colors isshown in Figure 2 above . A10bit LVDS input is transformed by an internal T-con look-up table intoa 12bit digital code for the 12bit linear DAC inside the driver IC.
PPDS digitalgamma. A digital gamma system is compared to a traditional onein Figure 3 below . Atraditional system reproduces digital data in 8bit colors through anRladder installed in the driver IC.
|Figure3: The digital gamma system is compared to the traditionalsystem.|
In the digital gamma system, the existing gamma information in thedriver IC is realized in 10bits by the look-up table. The 10bit coloris reproduced by a linear DAC in the driver IC from an 8bit colorinput.
PPDS protocol. Information transmitted through data lines using the PPDS' protocol areshown in Figure 4 below. Information such as pixel inversion, charge share time, line delaycompensation, pre-charging setup and black frame insertion aretransmitted in the front of each line.
|Figure4: Information transmitted through data lines using the PPDSprotocol are shown.|
Horizontal line delay compensation. When a panel size is large,there is a signal delay due to the increase in the gate line load,which decreases with charging time. To prevent this, a gate driver ICis attached to each end, which, however, increases cost and recoversonly 50 per cent on the charging time.
PPDS' controls each IC or IC output by dividing it into six to eightoutputs at a time to protect charging time loss caused by the gatesignal delay. Therefore, there is no need to use gate driver ICs oneach end. The output of a source driver IC is also controlled as muchas a gate signal delay, minimizing charging time loss.
Deskew function. Deskew test is done in each line toselect the best clock/data delay, maintaining the configuration or databefore transmission.
Benefits of cyclic-DAC
DAC methods are divided intoR-DAC and cyclic-DAC for LCD driver ICs.R-DAC is a series resistance as shown in Figure 5 below , where output voltageis selected in accordance with digital rate. For a 10bit R-DAC, thereis a 2 x 1024 R-ladder as shown in Figure 5a.
|Figure5: R-DAC uses a 2 x 1024 R-ladder, cyclic-DAC transfers outputs byrepeating sampling and holding through a switching motion.|
For R-DAC, R-ladder size becomes larger, depending on the number ofgrey bits. For the 10bit R-DAC, the size of R-ladder becomes quadruple,larger than the 8bit one.
To cope with the increase of the size, there is a new interpolationdesign method. The cycle-DAC transfers outputs by repeating samplingand holding through a switching motion with two capacitors.
Small chipsize. The biggest benefit of using cyclic-DACs is that the ICsize does not increase with the increase of grey bits. All thanks tothe stacked structure of the cyclic DAC consisting of two DACs—oneupper and one lower—as seen in Figure5b above . Each DAC has two capacitors,and can reduce IC size, regardless of the number of bits.
|Figure6: The 12bit cyclic-DAC is much smaller than the 10bit R-DAC.|
Low powerloss. The buffer amplifier, as seen in Figure 6 above is the biggest powerconsumer in the driver IC. The simple design of the cyclic-DAC bufferamplifier results in significantly reduced power use.
Low chiptemperature. Chip temperature decreases with lower power use.Temperature comparison at the same conditions shows that thecyclic-DAC's temperature at FHD/60Hz was 10°C lower than for R-DAC.When the IC temperature is low, there is no need for a top case contactand a heat sink pad.
|Figure7: The 10bit R-DAC forms an 8bit R-ladder, switching additional2bits to make a final output of 10bits.|
Low outputvoltage tolerance. To reduce the chip size, the R-DAC takes aninterpolation design. As seen in Figure7 above , the 10bit R-DAC forms an 8bit R-ladder, switchingadditional 2bits, making a final output of 10bits.
The resistance tolerance and the interpolator tolerance affect AVO(output voltage deviation among driver ICs) and DVO (output voltagedeviation within driver IC), but in cyclic-DAC, only a capacitancetolerance exists. As this is much smaller than resistance tolerance, itshows more accurate output characteristics.
|Figure8: The structure of cyclic-DAC is shown. Each channel has twoDACs.|
Fewer gammareference voltages . As the cyclic-DAC decides the output voltageby switching, the number of gamma reference voltages is 6, which ismuch smaller than the R-DAC's, and it is independent of the number ofgrey bits.
On the contrary, the R-DAC needs 18-22 reference voltages for10bits. As the number of reference voltages is becomes smaller, itfollows that PCB size becomes smaller. Less cables and connector pinsalso help reduce BOM cost.
Fast settingtime. The cyclic- DAC structure is shown in Figure 8 above . Each channel has 2DACs. When the first DAC is converted, the second DAC is driven,holding the converted data to a standstill at the beginning of theoutput stage.
The R-DAC, as shown in Figure 9below delays rising/falling as the R-ladder, a decoder and anamplifier, need to be transacted in order.
|Figure 9: Settling time in the R-DAC is compared to cyclic-DAC.|
Reliability of poly capacitance
Many engineers think the tolerance or reliability of capacitance isworse than resistance. However, based on the measurement and analysisof reliability and matching of R-DAC and cyclic-DAC on 1,000 wafersused for driver ICs, poly capacitors are better than poly resistors.They provide output that is more accurate.
PPDS is good for designing thin PCBs as it has less data linesconnecting T-con to the driver ICs. It can also send more informationto the driver ICs using a novel data line protocol.
Also, PPDS' features horizontal line delay compensation and deskewfunctions that are helpful in securing pixel charging time andtransmitting/receiving data safely.
Edward Yi is display ApplicationSenior Engineer at STMicroelectronicsKorea
PPDS' is a registered trademark of National Semiconductor Corp.