Using precision analog MCU Peripherals to create high value, signal-intensive designs -

Using precision analog MCU Peripherals to create high value, signal-intensive designs


Editor’s Note: In this Product How-to design article, Pedro Pachuca and Tom David of Silicon Laboratories use the company’s SiM3U1xx/SiM3C1xx Precision32 MCUs to demonstrate how techniques such as high-precision PWM, fine PLL adjustment, and high-precision IDACs increase the value of 32-bit mixed-signal MCUs in applications that involve radio and motor control technologies.

General-purpose 32-bit microcontrollers (MCUs) are ubiquitous in the interconnected, sensor-rich embedded world in which we live. The proliferation of embedded intelligence and connectivity in virtually all aspects of our lives has led to a universe of increasingly capable 32-bit MCUs with more precise onboard sensors.

Motor control, radio control, audio sample generation and waveform generation using digital-to-analog converters (DACs) are typical applications that require MCUs with higher precision analog functionality. Because MCUs are not natural companion devices for radios, they often require specialized high-precision analog components or peripherals to be “well-behaved” in the presence of radio signals. End products involving radio or motor control technology generally benefit from the use of MCUs with high-precision peripherals and system IP.

For example, a motor controller with a high-precision pulse-width modulation (PWM) generator is able to control a motor more efficiently, thus saving power and increasing the lifetime of the motor. A radio system with an MCU containing a finely-controllable phase-locked loop (PLL) requires fewer external resources to reduce signal interference, resulting in a better end user experience and higher value. In short, 32-bit MCUs with best-in-class precision-analog peripherals can impart higher value to a wide range of applications.

PWM engine with high-resolution capability and safe-state functionality
A typical MCU almost always contains a PWM signal generator. These signal generators are useful when coupled with external resistor-capacitor (RC) networks for generating audio tones or other sinusoidal waveforms. PWM signals are also used to drive motor control circuits. Thus, placement of the PWM edge can be crucial in generating a smoother sinusoidal waveform with finer frequency and phase control and controlling a motor to a finer degree of efficiency.

A typical motor-control capable PWM engine generates both center- and edge-aligned PWM signals. It also supports a differential mode capability with dead time insertion for applications requiring a “break-before-make” capability. The typical PWM signal generator should have a resolution of at least the highest operating frequency of the device.

For example, in the case of SiM3U1xx/SiM3C1xx Precision32 MCUs from Silicon Labs, the PWM generator runs at a maximum frequency of 50 MHZ, allowing PWM edges to be generated with a maximum resolution of 20 ns. These 32-bit MCUs also implement a mode in which the PWM edge can be placed on both edges of the highest operating frequency clock of the device, resulting in an edge resolution of 10 ns as shown in Figure 1 . This degree of resolution is more than sufficient for most non-power-supply-related applications.

Figure 1. 10 ns Edge Resolution for PWM Generator

Another key capability in a motor control (or other high-speed control) system is the ability to shut off the motor in the face of some catastrophic external or internal event, such as an over-current condition. This “kill” capability should shut off the PWM engine, place the control signals in a known good state and configure the I/O pads to a known good state to prevent damage to external circuitry.

The SiM3U1xx/SiM3C1xx MCUs contain six high-drive pads capable of driving up to 150 mA each or 400 mA total. If all the pads are driven simultaneously and left uncontrolled, external circuitry can be damaged. The high-drive pads can be used in conjunction with the PWM engine to directly drive small motors. In the event that a kill signal is received, the high-drive pads have a “safe-state” function that causes the pads to revert to one of three preprogrammed states: tri-state, pull high, or pull low. These safe-state configuration registers are only reset upon system power-up and otherwise remain undisturbed once written by software and locked. Any other reset does not affect them.

Fine PLL adjustment capability
In a typical MCU/radio integrated device, noise mitigation is a key consideration in using the radio effectively. In these integrated applications, it is common to find the microcontroller shut off altogether when the radio is in receive mode, depending on the use case in transmit mode, to avoid noise pollution from the MCU. If the radio is a frequently used device, the impact on MCU performance can be severe.

One way to mitigate this effect is to change the MCU’s frequency of operation to ensure any noise spurs generated by its clock appear outside of the radio band of interest. This implies having a fine tuning granularity in the MCU’s PLL such that its frequency can be modified to place these noise spurs outside the radio’s band of interest.

The PLL used in Precision32 MCUs provides the capability to move its frequency of operation in approximately 200 kHz steps between 23 and 80 MHz. This fine resolution simplifies integration of the SiM3U1xx/SiM3C1xx MCUs with any radio device without suffering a performance loss due to massively degraded frequency of operation or event cycling.
DMA to everything
Direct memory access (DMA) is a mechanismcommonly employed to move data between memory and peripherals. Thistechnique relieves the CPU of this trivial task and frees up more MIPSfor other useful work.

A typical DMA implementation on an MCUhas a fixed number of sources and targets on the device, thusrestricting the usefulness of the DMA engine. Given the nature of ageneral-purpose MCU, it is difficult to predict which peripherals needDMA. The general rule is to apply DMA to the high-bandwidth peripheralsand ignore all others. However, in a real-time system, it can bebeneficial to provide DMA access to all addresses on the machineregardless of bandwidth.

The SiM3U1xx/SiM3C1xx MCUs, for example,implement just such a system. While only a certain number ofperipherals have explicit DMA support (i.e., they can be configured asDMA masters with FIFOs and interrupt logic to support detailed bandwidthmanagement), all peripherals can be accessed by the DMA. Thoseperipherals without explicit DMA support must be bandwidth-managed insoftware and will not have a mechanism to signal back to the CPU in caseof a buffer error condition. For example, the port pulse generator canbe controlled by just such a system with some software overhead, thusenabling an arbitrary waveform generator that can be controlled moreprecisely.

This DMA engine can also be used to control the MCU’sPLL using DMA-chaining based on radio traffic. For example, if the radionotifies the MCU that it was about to transmit a packet, a software DMAtrigger can be used to issue a DMA request that will load the PLL withrelevant parameters that shift its frequency, thus reducing its radiointerference footprint.

Higher precision current DAC
ADAC generates an analog voltage when presented with a digital code. Atypical DAC will have a certain bit-precision that it can achieve,depending on the design. Thus, a 10-bit DAC will convert a 10-bitdigital code into a voltage (or current) in a given range.

DACsintegrated on MCUs can be used for many purposes, such as bias currentgenerators, arbitrary waveform generators or, in the case of a currentDAC (also known as an IDAC), as a relatively noise-immune communicationmedium.

Given the waveform generation capability of a DAC, atypical implementation allows the DAC to have DMA accessibility andfunction as a DMA master with a concomitant FIFO. This arrangementallows waveform generation using the DMA from a defined waveform inmemory, for example.

The SiM3U1xx/SiM3C1xx MCUs take this DACconcept one step further. A FIFO structure implements a loopingcapability that extends the precision of the IDAC from 10 bits to 12bits at one-fourth the data rate by interpolating between adjacent 10bit values without DMA intervention. For example, if the IDAC outputsthree identical values of “x” and a fourth value of “x+1”, the IDACoutput as measured at the package pin will be a 12-bit precision valueas shown in Figure 2 . This capability can be used to generate a 12-bit precise bias current.

Figure 2.12-Bit IDAC Output

Techniques that extend the precision ofstandard analog capabilities increase the value of 32-bit mixed-signalMCUs in applications that involve radio and motor control technologies.The high-precision PWM engine, fine PLL adjustment, and high-precisionIDAC exemplify extended precision capabilities that provide 32-bit MCUswith more capabilities in applications that these devices couldotherwise not serve. DMA-to-everything is a capability that provides theMCU with more granular control and peripheral usage to further enhancevalue. Higher precision implemented in today’s 32-bit MCUs will almostalways lead to higher value through better usability and applicability.

Thomas David is a principal design engineer for Silicon Labs’ MCU products and wasthe lead designer for the company’s first 32-bit MCU product, theSiM3U16X Precision32 MCU. He has been involved, either as a designer oras a chip lead in nearly all of the MCU products released by SiliconLabs. He came to Silicon Labs as part of the company’s Cygnal IntegratedProducts acquisition in 2003. Prior to Cygnal, he was president ofSilogix, an Austin-based silicon intellectual property (SIP) companythat was acquired by Cygnal Integrated Products. He has a BSEE fromPurdue University and an MSEE from Penn State University.

Pedro Pachuca manages Silicon Labs’ global microcontroller(MCU) interface product business. He joined Silicon Labs in early 2010.Previously, he was a product marketing manager at FreescaleSemiconductor where he developed MCU business strategies to penetratenew global markets and managed a business with an annual run rate inexcess of $250 million. Mr. Pachuca holds a BSSE degree from theInstituto Politecnico Nacional at Mexico City.

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