This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
Today's designers of utility meters and data collection systems facecomplex demands as the need for sophisticated utility distributionmanagement grows.
Whether you are involved with the design of AMR (automatic meterreading), power quality meters, or energy monitoring systems for water,natural gas, or electricity utility systems, ferroelectric randomaccess memory (F-RAM) offers the system a way to write data tonon-volatile storage instantaneously. Floating gate technologies(EEPROM and Flash) use a write-back page buffer and have long writedelay times.
This is a potential problem during a power outage when critical datamust be stored into a non-volatile memory immediately. Utility metersmay need to record data prior to a power outage. The effects of thisdata loss can result in significant monetary loss for a utilityprovider. Fast write speed is a significant feature of F-RAM memory formeter designs.
Since F-RAM memory features high endurance, the system's data can beread and written to F-RAM as though it is general purpose RAM storageinside the host microcontroller. Traditional on-chip RAM provides onlytemporary storage. And EEPROM offers a limited number of write cycles.F-RAM memory is not only non-volatile but also offers virtuallyunlimited endurance, eliminating the need for complex wear-levellingsoftware.
F-RAM and Processor Companions forMetering
The use of F-RAM in metering has been widely accepted. Ramtron hasdeveloped a set of products that integrate F-RAM and processorcompanion features. All Ramtron processor companion products integrateF-RAM memory with companion features, such as system reset, powersupply voltage detect, watchdog timer, tamper detection, early powerfail, and more.
For metering applications, these integrated F-RAM products (Table 1 below ) not only provide afast nonvolatile memory but also keep system parts count down, costsdown, and reduce board space by including useful features thatcomplement the system microcontroller.
|Table1. FM31x, FM32x, and FM33x Processor Companions for Metering|
Tamper Detect and Event Logging
Event logging and tamper detection are two important features of ameter design. The FM31x devices integrate two 16-bit event counters fortamper-detect or other event logging purposes.
Each counter has an input pin that is edge-triggered and polaritythat is user-defined. The event counter may be programmed to detect atamper event, such as the system's case or access door being opened.The counter is battery-backed so that even when power is lost, thedevice will detect and count tamper events.
|Figure1. Tamper Detect & 16-bit Counter|
In Figure 1 above , anormally closed switch is shown. The switch is tied to ground, whichtypically is a system case or chassis. The pullup resistor provides therising edge when the case or access door is opened.
|Figure2. Polled Tamper Detect to Reduce Current|
An improved tamper detect circuit is shown in Figure 2 above . The FM33x devicesallow the user to invoke a polled mode, which occasionally samples thepin in order to minimize battery drain. It internally tries to pull theCNT pin up and if an open circuit is pulled up to a VIH level, it willtrip the edge detector and increment the event counter value. Thecurrent contribution to the meter design is approximately 5nA.
The meter design can also take advantage of the ability of the FM33xdevices to store these counts in non-volatile F-RAM. If the designeither does not have a backup power source or if the backup sourcefails, then you still have the counts recorded. No processor overheadis needed.
Early Power Fail Warning
Most electronic systems use voltage-regulated power to provide a stablevoltage to guarantee circuit operation. An unregulated power supplyalways precedes the regulator. As the unregulated voltage varies, theregulated voltage remains stable ” to a point.
As the unregulated supply voltage drops, due to a failure or normalsystem shutdown, the processor and memory subsystem is better served byknowing well before the regulator drop out that power is lost.
An early warning mechanism (Figure3 below ) provides to the host processor of this event. Anon-maskable interrupt (NMI) is a means by which the host can preparefor an impending loss of power.
A simple voltage divider, tied to the unregulated supply, can beconnected to the companion's on-chip comparator that senses thiscondition. The comparator output PFO is tied to the processor's NMIinput. This high level interrupt can then invoke a routine thatperforms a critical task before power is lost.
|Figure3. Early Power Fail Warning|
System Reset and Voltage Detect
System supervisors typically provide a host processor with thedetection of power supply fault conditions and the independent checkingof software lockup conditions by using a watchdog timer.
The FM31x, FM32x, and FM33x Processor Companions provide a reset pin(/RST) to drive a processor reset input during power faults, power-up,and software lockups. Whenever the VDD supply is below a user-settablethreshold, the low voltage detect circuit holds the system in reset.The reset pin may be wire OR'd with another active-low reset if thedesign requires it.
A low power, battery-backed real-time clock (RTC) is integrated and canbe used in time-of-use (TOU) meters to log power usage overtime. TheRTC can be used to timestamp a tamper event or other event. The FM313xand FM33x devices also integrate an alarm which could be useful forsetting a flag or future event to trip the host processor.
All RTCs automatically switch over to the backup source when themain power is down. The backed up circuits draw no more than1microAmpere under this condition. For those designs that cannot use abattery, all Processor Companion devices are able to operate in backupmode from a super capacitor. An integrated capacitor charging circuitis provided on all companion devices.
Mike Peters is a Sr. ApplicationsEngineering Manager at RamtronInternational of Colorado Springs, CO. He heldthe position of chairman of the JEDEC JC42.2 SRAM committee. He holdsfive US patents and a BSEE from the University ofMichigan, Ann Arbor, MI.