Using RapidIO IP cores for faster interface design - Embedded.com

Using RapidIO IP cores for faster interface design

The need for intellectual property (IP) cores has increasedsignificantly as semiconductor gate counts have followed Moore's Law,doubling roughly every 18 months. Yet manufacturers' IP developmentschedules have remained static, forcing semiconductor companies tomodify their design process by incorporating IP from internal andexternal sources in an effort to keep up with the abundance ofavailable gates.

Compressed chip development schedules and increasingly larger chipsizes are requiring semiconductor vendors to rely heavily on IP vendorsfor standards-based IP and verification IP cores that simplify andspeed development time in order to meet aggressive product schedules.Supporting the demand for IP are standards for quality, delivery andon-chip protocols, all designed to ease integration by semiconductormanufacturers.

Standards-based IP
The need by semiconductor manufacturers to have access to a broad rangeof IP has fueled the growth of many technologies and standards in themarketplace. For board- and chassis- level connectivity bus-standardIP, such as PCI , RapidIO,HyperTranspor t and others, hashad the greatest acceptance, as it enables external connectivity tostandard interfaces and applies to numerous, diverse markets.

One example is the RapidIO standard, an established, scalable,open-standard, switched fabric, used by component manufacturers andOEMs in the wireless infrastructure, edge networking, storage,scientific, military and industrial markets. RapidIO is also one of theserial standards that is used widely in multicomputer, embedded,communications, signal processing, and other low-latencyhigh-performance systems.

Heavily involved in the creation of these standards, many of thesame companies are creating and marketing the RapidIO IP in order toleverage their in-depth working knowledge of the RapidIO protocol.

This IP fully implements the RapidIO protocol and is designed foruse by semiconductor manufacturers who see the tangible benefits ofincorporating reliable, high-performance RapidIO endpoints into theirproducts.

Chips from a variety of vendors ” native RapidIO endpoints fromFreescale and Texas InstrumentsandRapidIO switches from Mercury Computer Systems, Tundra Semiconductor,and PMC-Sierra, for example ” create an ecosystem that enables productdevelopers to build complete systems.

This robust ecosystem is driving the creation of new chips based onRapidIO IP, which can come in the form of application- specificintegrated circuits (ASICs) that add bridges that connect to otherstandards such as PCI Express and Ethernet, and processor buses such asAMBA and CoreConnect to the existingecosystem of switches and endpoints. In addition, many low-volumecustom requirements can be met with field-programmable gate arrays(FPGAs) that connect RapidIO to a variety of custom functions.

Secondary IP markets
When a critical mass of corporations embrace a new standard and a largeenough investment of resources in silicon products takes place, asecondary market naturally emerges for other companies wanting toconnect to the established infrastructure.

In the past, reaching critical mass has been hampered by theenormous effort and cost required to develop and test the IP beforeconnecting it to a standard bus. This barrier is being dismantled by IPproviders who offer a fully tested and validated IP core forincorporation into any silicon.

In the case of RapidIO, for example, companies can use an IP core toincorporate a RapidIO endpoint without the years of development timeinvolved in design, verification, and validation.

However, the quality of the IP must be proven before it is adopted,because ASIC re-spins are cost-prohibitive.

Verification testing
Once a company has introduced a bus standard such as RapidIO into itsdesign, it must be tested to ensure that the interconnection of the IPto the company's core logic is correct. Verification IP is a crucialaspect of quickly and thoroughly testing the IP integration into thedesign. A typical systemlevel verification environment used to test theusers design is shown in Figure 1,below.

Figure1. System Verilog test bench environment

Many verification IP providers offer a set of standard-directedtests to prove basic functionality. This is especially useful instandard bus interfaces like RapidIO, because a significant amount ofprotocol knowledge is embedded within these tests. When choosing apartner for verification testing, it is important to evaluate eachvendor's expertise in the protocol at both the specification and systemlevels, where users have gained extensive knowledge of the protocol inrun-time systems.

A verification environment should include the capability to easilygenerate tests, which can create traffic patterns that users wouldexpect to see in the system. These tests, when randomized, allowextensive testing of the protocol IP to be integrated into the users'design without a large time investment. If the verification IP andprotocol IP are purchased from the same vendor, the integration time isshorter, better results are obtained, and communication is simplifiedby having a single point of contact.

IP delivery standards
The lack of standards for IP delivery has made the integration ofexternal IP more difficult and time-consuming. This problem has beenrecognized by the industry and IP standards are being developed tofulfill this need. The Spirit Consortium, for example,is working on a new standard mechanism for delivering IP.

This consortium is an industry- level cooperative that is developingspecifications for IP description and tools. It has defined anXML-based flow that enables the IP provider to deliver documentation,configuration, HDL, and high-level behavioral information in a singlestandard.

The goal is to provide developers with enough information to programthe EDA tools to integrate the IP into the chip in the best way withminimal effort. The decisions required to configure the IP can beextended to the verification IP, thereby allowing the verification IPto be configured to meet the exact needs of the design IP that wasconfigured by the tool.

The IP marketplace is maturing quickly after years of lacklusterperformance. This growth is driven largely by the need forstandards-based IP and verification IP cores that can significantlyreduce the time and effort involved to include these standards in endproducts. The growth of IP and the ease of its integration are furtherenhanced by standards for IP quality, delivery, and onchip protocols,such as the Virtual Socket Interface Alliance (VSIA),The Spirit Consortium, and the OCP/IP trade organizations.

Charles Frazer is an IP Systems Application Engineer with Mercury Computer Systems, Inc.

To read a PDF version of thisstory, go to “ RapidIOIP cores readyto provide a path to faster interface design.

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