High speed design has brought a set of design challenges that do not exist in lower speed designs, or exist at levels that don’t cause problems,. The ever-increasing clock speeds and edge rates have turned digital switching circuits into some rather good RF generators whichis not a good thing, of course! Other problems begin to manifest at higher speed as well: signal integrity problems due to impedance variations; power integrity problems that can cause switching failures or overheating.
There are two basic methods to ensure designs will function as intended and also meet EMI radiation requirements. The traditional method was to carefully follow established design rules and, through visual inspection, determine that the board adheres to those rules and is likely to function and pass EMI. Then a physical prototype is used to verify function and EMI compatibility. For lower-speed or less complex designs, this may still be adequate. But for complex and/or very high-speed designs, more assurance is needed.
Simulation is the second method of ensuring that designs meet requirements. Until recently, simulation was complicated and expensive, and usually required a specialist to execute it. The process often took overnight or even days.
Now new tools that are exceptionally easy to use can be integrated into design flows, taking data from the CAD system and running simulations. Tools are available to perform signal integrity (SI), power integrity (PI), and EMI checks using design rule checking (DRC). In this article, we examine EMI simulation and control, a common problem, as an example of how simulation can save time and cost by catching issues that would mean a design respin if a physical prototype was used. Figure 1 illustrates how simulation can provide both early prevention and early detection of problems that could be very costly.
Until processors began running in the hundreds of MHz and up, little attention was paid to EMI in most circuit designs. As clock speeds have increased to beyond 1 GHz, the fast edge rates on signals, coupled with the high volumes of low-cost electronic devices, have made electromagnetic compatibility issues extremely common.
Since 1982, the FCC has required that all electronic devices used in the United States pass standard EMI tests for radiated emissions. But even in devices that can pass the test some radiation remains, meaning EMI can reduce signal margins and increase susceptibility to outside noise. Most of these problems can be avoided simply by making sure all currents are travelling in a closed loop.
Visualizing return current involves a departure from the more intuitive notion of current travelling in a wire at DC (0 Hz) to thinking of current being transferred through electromagnetic fields at higher frequencies. Figure 2 shows a PCB trace and how its energy is into its reference planes through electromagnetic fields. The amount of energy transferred to the reference plane is proportional to the distance to each reference plane, as shown in the figure.
Whether the planes are at ground or a voltage plane, the trace will be coupling energy into its reference planes. The best case is if those planes happen to be the power and ground planes used by I/O buffers driving that trace, as this best accommodates a complete loop for the return current.
Using circuit theory to understand the current loop, it’s easiest to view the side of the trace and its reference planes using , illustrated in Figure 3. Chopping the trace into very short sections allows each section to have an associated inductance and capacitance per unit length. As the signal propagates through the trace, it is effectively charging up each of the LC circuits, and then moving on to the next one, charging that one up, and so on.
The inductance and capacitance are specified “per unit length”. Those inductance and capacitance values are determined by the propagation of fields between the trace and reference planes, and the values can be determined for trace structures using the HyperLynx field solver. In fact, field solvers are used to determine the trace impedance (the square root of L/C) and propagation delay (the square root of L*C).
With this model, it’s clear how current loops from the trace back onto the planes. In this example, since there are two reference planes, there are two loops in parallel. Within the trace, the current is usually referred to as incident current, and current in the planes is return current.
It’s important to remember that a transmission line is a combination of atrace and its reference plane. Keeping them both in good shapeeliminates most EMI problems. Breaks in the reference plane can causeproblems. Consider having a slot in the reference plane; some of thereturn current will surround the slot, as shown in Figure 4 .
Someof this current will be radiated. The break in the plane actually makesa nice slot antenna. In most PCB designs, this is unintentional and canlead to EMI issues. The best way to avoid creating unintentionalantennas is to keep the return current adjacent to the trace and on thereference plane(s).
An even more effective antenna is createdwhen the return current path is broken completely. This occurs when atrace crosses a split in the plane. Instead of the return currentfollowing an alternate path, most of it is radiated. This is a commonsituation in many PCB designs. Anyone who has used a 3D electromagneticsimulation tool to analyze a trace crossing a plane split and identifiedthe associated radiation levels knows that it is best to avoid such asituation completely.
There are a number of ways to work aroundtraces crossing reference plane splits. The best solution is to routeall signals referenced to a solid ground plane, but board thickness andcost concerns often do not allow this. However, through careful stack-upplanning, you can route slower signals against any power planes thatwill be split up among multiple different voltages. Even if this isdone, it usually involves a dual stripline trace structure, whichutilizes two reference planes for two trace layers. A trace will be moreclosely coupled to its nearer reference plane, allowing it to cross asplit in the further reference plane. As previously shown in Figure 2,the return current distribution scales linearly with the distance of thetrace to its reference plane. So, if a trace is four times closer toits nearer reference plane than the further plane, that plane will havefour times the return current.
A common method used to minimizeradiation from traces crossing plane splits is to stitch the planestogether in the vicinity of the trace crossing using decouplingcapacitors. This can be somewhat effective; however, it is important tonote that a mounted capacitor does not act as a low impedance across awide frequency band, so it will not eliminate the radiation issue.
Findingsuch issues often requires a tedious manual review of the layout. Butthese issues can be found quickly using HyperLynx DRC automated designrule checking tool. An example is shown in Figure 5 . Such design rulechecks can be automated and customized to go beyond just a simple checkof a trace crossing a split, to include an understanding of returncurrent distribution between two planes, and to check for stitchingcapacitors.
HyperLynxfrom Mentor Graphics is a simulation tool that allows investigation of ahost of potential problems in the context of printed circuit boarddesign. Now, HyperLynx DRC brings fast design rule checking tools toengineers and designers. HyperLynx DRC verifies complex design rulesthat are not easily simulated, such as rules for electromagneticinterference and electromagnetic compatibility (EMI/EMC). It includes 19standard design rule checks (DRCs) that can quickly and easily pinpointtrouble spots on the board that can cause issues with EMI/EMC, signalintegrity, and power integrity.
Custom DRCs can be written by oneor more designers, and with the DRCs, you can access all aspects of thelayout, including stack up, layers, planes, traces, vias, and pins.Additionally, you can manipulate and measure the desired geometries of adesign when performing a check, creating multiple what-if scenarios.
Otherissues can be found with HyperLynx DRC as well, such as thelow-inductance connection of decoupling capacitors in the vicinity ofthe power and ground pins of an IC. Decoupling capacitors are needed atICs to complete the return current loop even if there are no splits inthe plane. Referring back to Figure 3, only the piece of the currentloop related to the trace and planes is shown. The rest of the loop ismade up of the I/O buffer driving the trace. That buffer resides on theIC, and is connected to the trace through the chip package and pins, aswell as being connected to the power and ground pins.
Tocomplete the current loop, current will flow from the power pins throughthe buffer onto the trace. In a 0-to-1 transition, for instance,current will flow from the power pin, through the buffer and onto thetrace, then back to the power pin through the planes. If the trace isconfigured as in Figure 2 and located symmetrically between the twoplanes, half of the return current will flow into the ground plane andneed to make its way back to the power pin. This is where decouplingcapacitors placed at the IC allow that current to flow from the groundplane back to the power pin. That makes decoupling
capacitors as essential to controlling EMI as they are for maintaining power integrity.
EMIissues are related to both power integrity and signal integrity. Aninadequately designed power distribution network (PDN) will lead toradiated emissions, usually corresponding to the high-impedance pointsof the PDN profile. For signals, a signal radiating energy means thatenergy is not making it to the receiver, causing a signal integrityissue. This is usually manifested as edge degradation.
Signaland power integrity issues are usually solved through analysis andsubsequent design changes. Solving EMI issues involves ensuring completecurrent loops, which can be accomplished through careful inspection ofthe board. Reviewing all possible EMI issues on a board can becomplicated and time-consuming, but can be made more practical by theuse of automated design rule checks. Using HyperLynx in conjunction witha careful design review will leave your PCBs running reliably, quietly,and shipping on time.
Patrick Carrier worked as aSignal Integrity Engineer at Dell for 5 years before joining Mentor inSeptember 2005. Patrick is now a technical marketing engineerspecializing in analysis products, including signal and power integrity,EMC, and thermal design.