VadaTech announces the VPX571, providing dual agile RF transceivers, each based on AD9364. One channel includes a programmable filter on transmit. The combination of dual AD9364 with UltraScale+ MPSoC provides a complete transceiver solution for SDR and SIGINT applications, supporting both TDD and FDD operation.
The module is available with RF routed to front panel or to the rear via a VITA 67.2 connector. The AD9364 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands, and channel bandwidths from less than 200 kHz to 56 MHz are supported. The module is compatible with Analog Devices RadioVerse design tools to simplify radio development across a wide range of applications.
The module has 8 TX/RX SERDES, Dual GbE, 8 LVDS (could be configured as singled ended), CPU RS-232 and management RS-232 to the P1 connector. The FPGA interfaces to a single DDR4 memory channel (64-bit wide), allowing large data sets to be stored during processing as well as for queuing data to a host. VPX571 is based on Xilinx UltraScale+ XCZU15EG MPSoC FPGA, which has 3528 DSP Slices and 746k logic cells. The XCZU15EG includes a quad-core ARM application processor, dual-core ARM real-time processor and Mali graphics processing unit, as well as over 26 Mb of block RAM and 31 Mb of UltraRAM. The module also has on board 64 GB of Flash, 128 MB of Boot Flash and an SD Card as an option.