VDSL chip sets start below $7/port - Embedded.com

VDSL chip sets start below $7/port

Designers can implement Dynamic Spectrum Management (DSM) at a price point that's below $7 per port thanks to the Phybrwire series of very high-speed Digital Subscriber Line (VDSL) chip sets. Developed by ElectriPHY Corp., the devices provide up to 150 Mbits/s of aggregate performance, a power consumption below 1.0 W/port, and long reach performance (up to 5 km). The DSM technology enables the VDSL Physical Layer (PHY) engine to identify external noise on the line, such as crosstalk, and to dynamically adjust the frequency spectrum within a specified band plan. This adaptive capability lets the PHY continuously optimize line performance to accommodate the constantly changing conditions.

The series is made up of the Phybrwire 400 and Phybrwire 100 families. The 400 family is a two-chip solution, comprised of a four-port Advanced Digital Transceiver (ADX) and a four-port analog front end (AFE). It implements four bands of standards-compliant VDSL and is intended for traffic aggregation devices such as DSLAMS, optical networking units, access concentrators, and NGDLCs.

The 100 family is also a two-chip solution using an ADX-AFE combination that's been optimized for single-port, four-band VDSL operation. The family is aimed at applications that require low to medium traffic aggregation.

The Phybrwire products are sampling today. Production volumes will be available in the second half of the year. Reference design kits for both the families are available. For more information, visit www.electriphy.com.

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