Santa Cruz, Calif. — The next generation of functional verification will require new methodology, new tooling and industrywide cooperation, according to Mentor Graphics Corp.–and that company this week is un- veiling new moves in all three areas.
Mentor's Questa 6.2 simulation platform is adding a Unified Coverage Database (UCDB) that consolidates coverage data. The new Questa Vanguard Program includes more than 20 providers of training, intellectual property (IP) and EDA tools. And perhaps most significantly, Mentor claims that its Advanced Verification Methodology (AVM) is the first open, nonproprietary methodology that supports system-level-through-RTL verification.
AVM claims to be “open” because of how it's provided. The AVM Cookbook, available for free downloading by anyone, includes example code that can be cut and pasted into customer environments to build testbenches. Source code for base class libraries, utilities and implementation examples in both SystemC and SystemVerilog are available under an Apache 2.0 open-source license.
Mentor developed the methodology in cooperation with its customers and hopes to create an “ecosystem” similar to that around Linux, said Robert Hum, vice president of design verification and test at Mentor. “If there's one thing that will really help the industry make progress with next-generation verification, it's to have a cooperative effort where anybody and everybody who can contribute to verification has a forum to do it in,” he said.
A methodology is needed, said Hum, because verification contains so many technologies–including assertions, functional coverage, constrained-random testing, coverage-driven verification, transaction-level modeling and model checking. “How does a mere mortal learn all this stuff?” Hum asked. “A methodology that really helps people with the learning curve can let people be productive without spending two years in boot camp school.”
The AVM supports both SystemC and SystemVerilog, and the open-source code can run in any compliant SystemC or SystemVerilog simulator, Hum said. The AVM features an object-oriented coding style to reduce the amount of testbench code, and a modular architecture to enable reuse. But it doesn't require the use of object-oriented techniques, Hum said.
Mentor is not the first simulation provider to offer a methodology. Synopsys and ARM Ltd. last year released the Verification Methodology Manual, aimed specifically at SystemVerilog. Mentor says its AVM is distinctive because it also addresses SystemC, and uses what Hum called an “abstract adaptation layer” to link high-level models to RTL models.
This layer uses transaction-level models (TLMs) that can convert high-level packets to the individual pin signals needed at the register-transfer level. AVM follows the Open SystemC International TLM 1.0 standard. “TLMs act as the clutch in the transmission between high and low levels of abstraction,” said Hum. “This methodology allows you to connect architectural-level people all the way down to RTL people.”
AVM includes a test controller, coverage collectors, scoreboards, performance analyzers, stimulus generators, constraints, drivers, monitors and responders. AVM components use the same standard interfaces, thus easing modular testbenches and component reuse.
Single vs. multiple inheritance
Mentor says AVM offers additional functionality to address limitations in the languages. For instance, while SystemC supports multiple inheritance, SystemVerilog supports only single inheritance. In AVM, standard object-oriented programming techniques are used to implement the same interfaces and provide the same advantages of TLM that are offered by SystemC's multiple inheritance. Conversely, an AVM library of functional coverage components brings to SystemC a capability similar to the SystemVerilog “covergroup” construct.
The primary improvement in the new Questa 6.2 release is the UCDB. It is said to eliminate the complexity of gathering and managing coverage data for different tools by consolidating the data into a single repository. It can bring in data from other Mentor verification technologies, including 0-In formal verification tools and the Seamless hardware/software co-verification environment.
Because read and write APIs are provided, Hum said, users could also bring in coverage data for other vendors' verification tools, if they know what format those tools write. “Again, we're trying to create an open system here,” he said.
The UCDB handles all kinds of coverage data, including code coverage, toggle coverage, structural coverage, SystemVerilog “covergroup” coverage, Property Specification Language (PSL) cover directors, and assertion data. It claims to run at over 1 million insertions per second.
UCDB comes with a set of report generators, Hum said, and users can create their own custom reports using the read and write APIs. Users can close the verification loop by tying coverage results back to the original test plan.
Finally, Mentor's Questa Vanguard program includes companies that have agreed to work closely with Mentor to ensure that their products support the Questa platform and the AVM. Members include training firms, such as Doulos, Sunburst Design and Sutherland HDL; IP providers such as Denali Software; and EDA companies such as Averant and Real Intent.
“These are still early days for SystemVerilog, and we're trying to promote cooperation in the industry to get next-generation verification put in place,” said Hum.