The rising speeds and complexities associated with the latest memory technologies make them more difficult to debug and verify. A logic analyzer with memory support can make the process more straightforward.
Verifying and debugging memory-system designs that use DDR2 SDRAM is challenging because of the signal speeds, complex signal-timing sequences, and the many signals that need to be acquired and analyzed.
A logic analyzer with memory support gives the designer a powerful tool to verify and debug memory systems. The logic analyzer captures all the memory signals and shows the operation of the DDR2 SDRAM (Data Double Rate Synchronous Dynamic Random Access Memory) signals in a waveform window and a listing window. These two windows give designers insight into the memory system's operation, enabling them to verify and debug it.
The memory support:
- Configures the logic-analyzer channel assignments.
- Defines channel groups.
- Provides DDR2 SDRAM-specific state clocking.
- Defines command symbols used in triggering and bus forms.
- Decodes the mode-register bit fields.
- Decodes SDRAM commands into mnemonics.
- Displays read and write data in the listing window.
We start the memory analysis by using the logic analyzer's waveform window, which is similar to an oscilloscope's display, but displays large numbers of signal traces. When acquiring the signals of a 1-Gbyte, 240-pin unbuffered DIMM using DDR2 SDRAM, the logic analyzer acquires and analyzes over 90 signal traces (see the Table 1).
Figure 1 shows the waveform window of a DDR2 SDRAM's address, clock, commands, data, and data strobes. The vertical ticks in the top row of the waveform represent the logic analyzer's sampling resolution . The ticks are 125 ps apart, and the signals are sampled at 8 GHz. These marks show when the logic analyzer sampled the DDR2 SDRAM signals. It's important to understand that a high sampling rate provides finer and more detailed signal acquisition and analysis, versus using a lower sampling rate.
The logic analyzer's sampling resolution also defines the sampling uncertainty of the logic analyzer. In this example (Figure 1), the uncertainty in the measurement of the signal edges is 125 ps before the vertical sampling tick marks in the waveform window.
Individual strobe signals
For clarity, the logic analyzer organizes the signals into groups. Figure 1 shows single-channel waveforms for the memory-command signals DDRCK0, S1#, S0#, RAS#, CAS#, and WE#. Signal groups are used for address, data, and data strobes. The address group contains the 14 address signals and three bank address signals. The DIMM 64 bits of data are divided into most significant 32 bits of RdA_DatHi and the least significant 32 bits of RdA_DatLo. The strobes group contains eight strobes because there are eight DDR2 SDRAMs on this DIMM.
The state of the signals in bus form is represented by hexadecimal numbers. At cursor one, the center vertical dash line, the address state is 1B020, the most significant 32 data bits are 88888877, the least significant 32 bits are 77888877, and the strobes are 00. All the groups in Figure 1 have a plus sign (+) before the group name, meaning that signals are shown in bus form and can be expanded into individual waveforms. By clicking on the +, the individual signals are visible below the bus form with the eight strobes, as in Figure 2.
The bus form's cross pattern shows that there are signal transitions at that location in the waveforms. Expanding the bus form to the individual signals shows the details of each signal transition. The strobes' transition zone is 375 ps, which is measured by using the logic analyzer's user-defined markers. In Figure 2, strobes 0 and 2 transition first and strobe 4 transitions last. The same analysis can also be done on the other bus-form groups.
Figure 3 shows two separate waveform windows stacked one above each other. The top (write) window shows the timing of two 64-bit write-data words. The bottom (read) window shows the timing of two 64-bit read-data words. Notice the differences between write and read data-valid windows with respect to the cursors at the rising edge of the DDR2 SDRAM clock. Different data-valid windows for write and read data are common for DDR2 SDRAM. Write data is centered within the data strobes and approximately center-aligned with the clock edges. Read data is edge-aligned with the data strobes and approximately edge-aligned with the clock edges.
Also in Figure 3, the top write-window”command-group values are represented in hex, while in the bottom read window, the group values are represented in symbols. Using symbols reduces the effort needed to understand the timing waveforms.
Capturing the write and read in state acquisition requires configuring eight logic-analyzer sample-point positions for the eight data-valid windows that have their hexadecimal values underlined. State acquisition uses the rising edge of DDRCK0 with regard to the eight sample-point positions, to acquire all possible write and read data-valid windows in the DDR2 SDRAM clock cycle. After the logic analyzer stops its acquisition, the memory support decodes the commands and determines the correct sampled data to be used.
To effectively work between the waveform window and the listing window, cursors one and two are locked between the windows. Locking cursors provides an easy way to correlate the data between the waveform window and the listing window.
The listing window
In Figure 4, the listing window is the state-acquisition display of the DDR2 SDRAM signals that the logic analyzer acquired. The logic analyzer uses the listing window to show the state-acquisition data and to decode the command signals into mnemonics. The listing window has columns with logic analyzer's sample number, address, command mnemonics, 32-bit high and low data, and logic analyzer's time stamp of the sample. You can modify the listing window to show other data such as data mask, check bits, and bank address.
The listing window provides a higher logical view of the signals than the waveform window. One sample in state acquisition represents one complete DDR2 clock cycle. One sample in high-resolution timing represents 125 ps. In time duration, one state-acquisition sample equals 30 high-resolution timing samples.
DDR2 SDRAM burst their data in groups of four or eight. The burst length is configured by the memory controller in the mode register. In Figure 4, the burst lengths are four for the read and write commands.
A typical read-data sequence starts with an activate command, opening a row in a specific bank. Next, one or more reads are completed on columns in the opened row. Finally, the row is closed by a precharge command. A typical write sequence starts with an activate command opening a row in a specific bank. Next, one or more writes are completed on columns in the opened row. Again, the row is closed by a precharge command. By using a listing window you can quickly check the SDRAM for correct operation such as commands sequences, commands timing, burst length, and correct data.
A perfect DDR2-533 SDRAM clock period is 3.752 ns. For this example, the DDR2-533 SDRAM clock period is 3.744 ns. The logic analyzer used has a high-resolution timing of 125 ps and therefore the logic analyzer's time-stamp resolution is 125 ps. Hence, the time stamp between the state acquisitions is usually 3.750 ns. Sometimes it'll be 125 ps less (3.625 ns) or greater (3.875 ns). The time-stamp reference is from the previous displayed sample. You can select the time-stamp reference to a previous displayed sample, system trigger, cursor one, cursor two, or have it show absolute time.
Selective clocking stores DDR2 SDRAM data when commands are present and for 13 clock cycles after column-address assertion, resulting in more bus-cycle activity and fewer idle cycles being stored in the logic analyzer's acquisition memory.All or part of the listing-window data can be exported to a file. The data can be exported as an ASCII text file, binary file, or Tektronix TLA Data Exchange format. You can modify the exported data and load it into simulation programs or automatic-test-equipment systems.
The DDR2 SDRAM mode registers are programmed by the memory controller during the memory system's power-up configuration phase. The MRS command programs the mode registers using the address and bank-address signals. The bank addresses select the mode register and the address signals configure the mode-register bit fields.
By using the logic analyzer's conditional storage, you can choose to store only mode-register commands and, therefore, more efficiently use the logic-analyzer memory. Figure 5 shows the last of the mode-register commands that configured the DDR2 SDRAM. The listing-window's address column contains the bank's 3-bit address as most significant bits and 14-bit address as the least significant bits. The bank-address bits determine which mode register is configured with data on the 14-bit addresses. The logic analyzer decodes which mode register is being accessed and decodes the data on the 14-bit address signals into bit-field descriptions.
The mode register was programmed with both a latency and burst length of four. You can see this in Figure 4, where for the sample 154 read commands, the first word of read data on the SDRAM data bus is four cycles later (at sample 158). The two words contained on sample 158 occur because DDR2 transfers two data words per clock cycle and one logic analyzer's state acquisition on one DDR2 clock cycle. Notice that at sample 158, while the SDRAM transmits the two data words, the memory controller has also sent another read command to the SDRAM. Sample 154 read command (four data words) is in samples 158 and 159 because, as already mentioned, the burst length is four. The read command at sample 156 has its data on the bus starting four cycles later at sample 160 and completes its burst length of four with sample 161.
These back-to-back reads from sample 158 to 165 fully utilize the DDR2 SDRAM data bus at its full data rate. The read commands can't be sent in adjacent command cycles because every read requires two clock cycles to output its data. As a result, the fastest that the memory controller can send read commands is every other DDR2 clock cycle. If the burst length was eight, there would be three DDR2 clock cycles between each back-to-back read command.
DDR2 SDRAM write latency is the read latency minus one. Therefore, the write command at sample 138 has its data on the bus starting three DDR2 clock cycles later at sample 141 and completes its burst length of four with sample 142. The write command at sample 140 has its data on the bus starting three DDR2 clock cycles later at sample 143 and completes its burst length of four with sample 144.
Be aware that the DDR2 SDRAM's additive latency in the first extended mode register will add cycles between the read and write commands and their data. In this example, the additive latency is zero and no additional DDR2 clock cycles are added between the read and write commands and their data.
The logic analyzer is the tool of choice to verify and debug memory systems. The logic analyzer captures all memory signals and shows the operation of DDR2 SDRAMs in a high-level state listing window, as well as in a detailed timing waveform window that lets designers identify faults in the DDR2 SDRAM digital signals.
David Haworth is a logic-analyzer memory-application specialist at Tektronix. He was one of the founders of the VXIplug&play Systems Alliance and SCPI Consortium. Haworth can be reached at .
- www.tek.com/memory for memory application notes, e-learning and other memory related information
- www.nexustechnology.com for Nexus Technology memory supports for Tektronix logic analyzers and DDR2 white papers
- www.jedec.org for JEDEC DDR2 SDRAM specifications
- www.memforum.org for DDR2 Memory basics information
- www.micron.com for DDR2 SDRAM data sheets and application notes