CAMPBELL, Calif Final balloting for the next version of the RapidIO serial interconnect switched fabric architecture used in embedded computing is nearing completion having been underway since the spring.
“I hope to have it ready for our next face-to-face meeting in Austin on Nov 7, but then I am always hopeful,” said Tom Cox, executive director the RapidIO trade association. “You have to compare that with the years it takes to get something through IEEE spec development. I wouldn't say 2.0 is urgent and people are not using the full capability of 1.3.”
Changes in the 2.0 specification will concentrate on two major areas; a higher performance physical layer to provide the next step in bandwidth matching with current SerDes and enhancements to the data plane to provide carrier grade data fabric performance.
“We did it very carefully, we took probably eight pieces and had different groups develop them independently. These will be released as one spec update,” said Cox. “It is important to realize that this is not a new generation of RapidIO but added layers to the existing spec. You do not have to add the new capabilities to your products.”
Link width options are being extended with 2x, 8x and 16x being added to the existing 1x and 4x while signaling rates are being extended with 5.0 and 6.25 Gbaud joining the current 1.25, 2.5 and 3.125 Gbaud options. The 8x and 16x will not be used across the back plane, it will be used to connect two fabric chips on a board.
To build in the reliability required for carrier class operation, hot plug support is being provided at the electrical level so that boards can be removed without affecting the operation of a system. “We don't aim to reinvent the wheel,” said Bill Bean, chairman of the RapidIO marketing working group and a senior product manager at Integrated Device Technology. “We have made use of exiting electrical specs so that for speeds below 3.5 Gbaud we will make use of the existing 3.125 Gbaud Xaui (10G attachment unit interface) and the Optical Internetworking Forum (OIF) specs for speeds above 3.5 Gbaud.” Functionality is also being improved in control symbol and idle patterns that are built in to the spec.
In the data plane a new data streaming packet format will be introduced allowing enhanced carrier class capabilities while the addition of virtual channels to serial physical layer will further segregate the logical flow of data. An endpoint flow control arbitration specification will help with peer-to-peer transaction management while both traffic management and virtual output queuing will be improved.
The association is keen to maintain backwards compatibility to the last revision 1.3, released in June 2005. “By and large we will leave the core notation of common transport unscathed so we will have full operability back and forth between the generations of our standard,” said Bean. “Customers will be able to scale their solutions over time and newer faster products to operate with slower products.”
The RapidIO standard is defined in three layers: logical, transport and physical. The logical layer defines the overall protocol and packet formats. This is the information necessary for end points to initiate and complete a transaction. The transport layer provides the necessary route information for a packet to move from end point to end point. The physical layer describes the device level interface specifics such as packet transport mechanisms, flow control, electrical characteristics, and low-level error management. This partitioning provides the flexibility to add new transaction types to the logical specification without requiring modification to the transport or physical layer specifications.