Virtex-5 TXT ready for 100GbE - Embedded.com

Virtex-5 TXT ready for 100GbE

Telecommunications equipment manufacturers developing the next generation in Ethernet bridging and switching solutions for 40- and 100-Gigabit Ethernet (GbE) market are the target for the Xilinx Virtex-5 TXT field programmable gate arrays (FPGAs).

Xilinx FPGAs are already being used in the development of these new technologies, and by offering a single (programmable) chip Virtex-5 TXT solution today, Xilinx can help manufacturers to lower their costs while accelerating development of next generation 100GbE systems.

These must support multiple connectivity protocols, while also adapting to changes in the evolving standard for the interface between 100G optical modules and the media access controller (MAC).

The Virtex-5 TXT platform consists of two devices that deliver the highest number of 6.5Gbps serial transceivers available on any FPGA, and are fully supported with application-specific IP, development tools, and reference designs for implementing high-bandwidth protocol bridging.

Xilinx has used the ASMBL architecture first introduced with Virtex-4 FPGA to speed the development of the Virtex-5 TX. With its forty-eight 6.5Gbps GTX transceivers, the platform is optimized for 100 Gigabit Ethernet applications. It is designed to improve signal integrity for reliable operation of 10/100Gbps links, lower power consumption per channel for better reliability, and provide programmable support for multiple protocols.

The 600Gbps total bandwidth is required for building network bridges such as 100GbE to 120Gbps Interlaken, 40Gbps Quad XAUI to 50Gbps Interlaken, OC-768 to OTU-3 and SFI-5 to 4xSFI4.2.

The bandwidth, high-transceiver count and ability to support multiple standards on a single programmable Virtex-5 TXT device also makes the devices suited for high-performance computing and video broadcast applications.

In November of 2006, Xilinx FPGAs were used to showcase the world’s first successful 100GbE transmission through a live production network demonstrated at SC06 International Conference by Finisar, Level3 Communications, Internet2, and the University of California at Santa Cruz (UCSC).

In June of this year, telecommunications services giant Comcast Corporation announced the successful completion of a 100GbE technology test over its existing backbone infrastructure between Philadelphia and McLean, VA using the industry’s first 100GbE router interface. The system used Sarance Technologies’ High Speed Ethernet IP Core (HSEC) running on a Virtex-5 FXT FPGA, which is now available as part of the new Virtex-5 TXT solution.

The ISE Design Suite 10.1, service pack 3, provides designers access to the entire line of Xilinx FPGA logic, embedded processing and DSP design tools.

These include the ISE Foundation, Embedded Development Kit (EDK), System Generator for DSP, AccelDSP Synthesis Tool, ChipScope Pro and ChipScope Pro Serial I/O Toolkit, PlanAhead Design and Analysis Tool, and ISE Simulator. Also available are Synopsys HSPICE models, Mentor ELDO, Ansoft Nexxim, Agilent ADS as well as Mentor SI tools.

Third-party IP available for use with the Viretx-5 FXT includes the Sarance Technologies: 100G Ethernet, 120G/50G Interlaken; Avalon Systems’ SFI-5, OC-768, OTU3, EFEC, GFE and MorethanIP’s RXAUI, 10G Ethernet, 2.5G Ethernet, Ethernet switching IP.

Virtex-5 TXT is part of the broader Virtex-5 family rollout, which started in 2006 and includes the LX, LXT, SXT and FXT FPGA platforms of domain-optimized architectures.

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