Santa Cruz, Calif. — Silicon virtual prototyping (SVP) tools once promised to greatly accelerate ASIC design, but most of the original providers have disappeared. Diana Raggett, president and CEO of startup Javelin Design Automation, believes the time has come for a second generation and a fresh approach.
Javelin (Saratoga, Calif.) this week will announce its mission to provide “system physical prototyping” (SPP) tools that bring together architectural, logical and physical IC domains in one environment. The startup, which claims to have a working tool that has amassed customers and tapeouts, says its software will shorten design cycles and improve the quality of results. By linking architectural design with physical implementation, the Javelin tool promises to give designers accurate physical information for making key decisions early in the design cycle.
SVP was the technology that was supposed to raise ASIC signoff to the register-transfer level (RTL), and it was a theme at the 2001 Design Automation Conference. But most of the companies carrying the banner at that time–including Icinergy, InTime Software, Tera Systems and Monterey Design Automation–have folded. Javelin, in fact, purchased Icinergy's assets shortly after the Javelin launch in 2004.
In its 2005 EDA market trends report, Gartner Dataquest surveyed the SVP market and reported that “EDA users still have no good solution for this very important tool.” The report found that some ASIC vendors had already gone back to internal tools. Dataquest ranked Cadence, which purchased Silicon Perspective Corp. (SPC), as the dominant SVP tool provider.
Javelin's Raggett insists the time is ripe for its SPP approach. Compared with five years ago, she said, chip design has become much more complicated, and market windows have tightened. “Where any- body is pushing anything in a tight window, they need [SPP],” she said.
Raggett said SPP goes beyond the first-generation SVP tools in a number of ways: It starts much earlier in the design process, can accept incomplete data, is easier to use and is more accurate. Javelin is so optimistic that it predicts a total available market of $500 million to $800 million–a far cry from Dataquest's estimate of a $152 million SVP market in 2009.
EDA veteran John Cooper, who was majority owner of Icinergy, thinks Javelin has a bright future. “I think what Javelin brings to the table is the ability to get some good feedback on physical design,” he said. “That's something you can't throw over the wall any more, so if you can get feedback on what the timing will be early in the design, I think that's going to be key to [Javelin's] success.”
Raggett founded Javelin in 2004 with Koko Mihan, vice president of engineering, and husband Matthew Raggett, a director. Matthew Raggett was president and CEO of Analog Design Automation before that company's sale to Synopsys. Penny Herscher, former chairman and CEO of Simplex Solutions, is also on the Javelin board.
Mihan led engineering at Icinergy. Several other Icinergy de-velopers, working at Javelin's R&D facility in Ottawa, are among Javelin's 10 employees.
Diana Raggett spent 10 years in marketing at Cadence, where she noted that design teams had no tools for collaboration: “My passion was to really bring a platform together that enables the best minds in a company, whether in architectural, logical or physical design, to work together.”
In the absence of SPP technology, Javelin said, customers are making high-impact decisions with little or no physical insight. RTL designers, for their part, must implement blocks with no chip context or physical feedback, and layout teams have to tape out with infeasible chip architectures. The repercussions include silicon respins, iterations and compromised cost or performance.
With early chip-level optimization, Javelin claims, customers can improve chip architecture by more than 40 percent, boost RTL coding by 20 to 40 percent and improve RTL synthesis by 10 to 20 percent.
Shortly after the Javelin launch, the founders started talking with Icinergy's Cooper. They decided Icinergy's SoCarchitect software, which offered floor planning along with timing, power and area estimates, would be a good starting point.
But it was just a start, Diana Raggett said. “For us, it was like acquiring the chassis and wheels of a high-performance car we wanted to build. It allowed us to focus our development efforts on the high-performance engine.”
But why didn't the technology take off in the first place? “I think [Icinergy] had good technology, but they stayed at the floor planning and estimation area,” she said. “It didn't go deep enough. It was a nice-to-have, not a must-have. That's partly because it was a solution before its time.”
Cooper echoed the sentiment: “Icinergy had good technology, but people were just not quite ready for that technology.”
The first-generation SVP providers, Raggett said, fell into one of two pitfalls. Some tools were easy to use but too light on capabilities; others offered more detail but were hard to use and difficult to correlate with logic synthesis. Customers, she said, complained about lack of accuracy.
“We start from the earliest stage of the design process, at the architectural or system level, while a lot of [SVP] systems started post-netlist,” Raggett said. “The second thing is that we've made our technology very easy to use. Third, we designed Javelin to work with partial or incomplete data. Previous solutions that did that lacked accuracy, customers told us.”
With an official product launch slated for late summer, Raggett declined to give details of the Javelin tool. She did note that it encompasses SVP technology by offering constraint-driven floor planning and placement. But it does not include a fast synthesis capability, which was offered by many of the first-generation SVP tools.
Using both graphical and textual input, she said, the Javelin tool offers a “sandbox” in which customers can quickly run what-if analyses on many architectures and implementations. The tool addresses such market segments as consumer, communications, wireless, computing and storage-area networks.