What to do when your SPICE models run out of gas: Part 2 - Embedded.com

What to do when your SPICE models run out of gas: Part 2

Most SPICE versions are not optimized for the analysis of serial ordifferential signals. Certainly serial and differential can be handledby any SPICE simulator, but that is not the same as being optimized forsuch signal integrity applications.

When you need to measure the differential voltage at a particularpoint in a circuit, you are not yet likely to find a “Vdiff” functionin your SPICE simulator. You are goingto have to define this by hand.If you want to plot the common-mode signal, again you must define ityourself. Of course now that it is printed in a book, the programmerswill put it in.

Differential signaling enables very high data rates on circuitboards. But traditional techniques for controlling skew and fordistributing clocks run out of gas at these speeds. The answer is oftenembedded clocks and de-skewing inside the silicon.

A typical embedded clock is implemented by encoding the data in sucha way that there is a guaranteed minimum transition rate, or number ofsignal edges per unit of time. Then, a phase-locked loop can be usedwith this data to recover the clock.

In the days of parallel buses, the skew between the data lines andbetween the data and clock were a major concern. Skew is the differencein flight-time for the various individual traces.

Even if the lines were all carefully laid out to be exactly the samelength, variations in the dielectric constant in the board materialcaused skew. As bus rates increased, skew became a factor limiting themaximum usable bus rate. The reason was the way data was strobed intothe receiver.

The parallel data would arrive at each of the bit latches and whenall had settled and were stable, the clock or strobe would trigger allthe latches simultaneously to capture the data. If some were earlierand some later, all would have to wait for that last bit to be ready.The range of arrival times for the individual bits became a majorlimiting factor on how fast the bus could ultimately run.

In high-speed serial systems, de-skewing is done electrically ratherthan mechanically. De-skewing can be done by mechanisms such asmeasuring the time-offset of each input and selecting a particularclock phase that best matches it. It is fairly easy to generate a rangeof clock phases to facilitate this.

This method in turn necessitates a circuit training plan in whichthe relationship between clock and data can be measured. As the arrivalphases of the individual signals are identified, the optimal clockphase for each can be locked in. So, the issue of skew betweendifferential pairs that are not within an individual pair has passedinto the realm of non-issue.

Because perfect components, components with no time delay and noparasitics, come naturally to SPICE, it is very easy to set up adifferential driver—two outputs with complementary signals. Of course,there are a few standard warnings. As in any modeling task, be sure toinclude appropriate parasitics. For example, the tool can quite easilyimplement a behavioral driver that has no capacitance to ground.

In the real world, such a thing will never exist. As is typical ofdriver models, the important things to get right are the output voltageor current swing, the rise and fall times, the impedance, and thecapacitance. In addition, differential drivers have both common-modeand differential impedance, and these can be independent of each other.The point is, take care to get them right.

Differential Receivers
Just as SPICE doesn't inherently recognize differential drivers,neither does it recognize differential receivers. Again, you aretypically going to have to build the model. It is fairly easy to dobecause primitives such as the voltage-controlled voltage sourcealready embody most of the characteristics needed in an idealdifferential receiver.

All the model needs is appropriate parasitics, terminationimpedances, capacitance, and so on, and you can use it as yourreceiver. At this time, non-linearities and dynamic range will not becovered because the target of this book is the interconnect circuitryrather than what goes on inside the silicon.

Figure7.8. A SPICE Ideal Component to Monitor Differential Voltage

Signal level and phase arriving at the receiver are usually criticalparameters in any high-speed link. Viewing the differential signal iseasily achieved through use of an ideal voltage-controlled voltagesource, as in Figure 7.8 above.

In the case of using such a device to monitor a differential signal,all parasitics are left off so that the source produces infiniteimpedance at the point of measurement, and the gain is usually set toone. As such, it is possible to make measurements in SPICE that cannotbe made in the real world.

Alternately, many versions of SPICE have the capability to do mathon signals, so the differential voltage can simply be defined as anequation. Placement of a physical probe on a line always addsparasytics.

At microwave frequencies, the added parasytics, indicated in Figure 7.9 below , are usually fartoo large to ignore. That makes it difficult to measure waveforms thatexist on the line when the test probe is not present.

Figure7.9. Parasitics Added for a Voltage Probe

Two solutions are possible. One is to get or generate a good modelof the test probe, and run a simulation with the probe model in placeto correlate what is measured with what is there when the probe is notpresent. An alternate is to use a receiver designed to measure thesignal quality at its inputs. A third alternative that actually workswell in the frequency domain is to electrically characterize the parts,packages, and so on and calculate the result.

Differential Transmission Lines
Almost everything can be modeled. Recall the “T” line that came withthe original SPICE implementations. This was an ideal transmissionline. It had no loss.

When it was used, you did not have to calculate aninductance-capacitance ratio that would yield the desired impedance andvelocity; the “T” model made that unnecessary. It simply asked for thedesired impedance and delay. That level of support for differentialtransmission lines does not yet exist in most SPICE tools.

Among the parameters that you might like to see in your modelingtool is the ability to accept a transmission line definition in termsof differential and common-mode impedance, loss per unit of distance,and delay. The fact that such facilities as these are not there doesnot stop you from performing simulations; it merely adds a bit morework to include them by hand.

Of course, eventually all of this work might be bypassed by theenabling of S-parameter models in SPICE. Again, in an ideal world youwould work entirely in the frequency domain. Components would becharacterized by their S-parameters, and the response of the entirecircuit response would be calculated by applying chaining to thevarious elements of the interconnect.

In this ideal world, circuit simulation would not even be needed.The response would be mathematically generated from measured orsimulated frequency domain models  – S-parameters – and noiterative procedures would be required. Rather than simulation, therewould be an extremely fast mathematical procedure.

Unfortunately, that ideal is not the world as it is. The problem islinearity. You cannot presume that the voltage and current sources arelinear. They are not. The interconnect circuitry might be reasonablylinear, but the silicon at the ends is nonlinear, at least to somedegree.

That nonlinearity makes it inadequate to examine the response onefrequency at a time. The actual response will have interactions betweenharmonics, and the response will be dependent on the amplitude andphase relationships between the harmonics. It becomes a modulationproblem.

But the interconnect, the packages and circuit board traces, arelikely to be linear in voltage response. The sort of thing that wouldmake these parts nonlinear would be the presence of magnetic material.Without magnetic material, the parts are linear.

That linearity makes it practical to solve the response of theinterconnect in the frequency domain using very fast analyticprocedures and then add the impact of nonlinear drivers in aniterative, time domain, analysis. The capability of using blocksdefined with S-parameters in time-domain simulations is just beginningto show up in SPICE tools.

One reason for interest in the frequency domain is this: Time domainsimulations often rely on iterative methods and so are relatively slow.Frequency domain solutions can often be achieved through analyticmethods and can be extremely fast and not iterative.

You can even see this in SPICE. Compare the time it takes SPICE tocalculate the time domain response of a moderately complex L-C circuitwith the time it takes to do a frequency sweep of the same circuit.

Corners and Bends
Corners and bends are unmodelable in the sense that SPICE does not havebuilt-in mechanisms to deal with them. The handling of a corner in anindividual trace is a bit more complicated than the handling of a bendin a differential pair. In the lower gigahertz frequencies, the impactof a corner in a trace is often so much less than the variability ofthe materials themselves—the manufacturing variables—that corners intraces can often be ignored.

As shown in Figure 7-10 below ,a square corner adds a small amount of capacitance; the amount can becalculated with a field solver—not by SPICE. The added capacitance issometimes the combined effect of added physical area and the reactanceof ephemeral modes produced by the corner discontinuity. The usual wayof modeling a corner in SPICE is to add a small discreet capacitor atthat point in the transmission line, add a small L-C-L segment, orignore it.

Figure7.10. Capacitance Added by a Corner

Bends are another issue altogether. Here we are using the word”bend” to refer to a differential pair's corner. The handling of a bendhas been already described, but more details may be useful. The mainthing that a bend does, but is not recognized by SPICE, is increaseemissions.

Conversion of some signal to common-mode by a bend can cause lossdue to radiation, and SPICE doesn't know about radiation. Usually thisis not a major cause of signal loss, but it can be a major cause ofemissions.

Planar Waveguide
The region between two metal planes can be described as a planarwaveguide. Examples of this type of waveguide, shown in Figure 7.11 below, exist on mostcircuit boards in the form of the region between power and groundplanes, or the region between multiple ground planes.

Figure7.11. A Planar Waveguide

Signals can be injected into this waveguide by applying a currentthat traverses the distance from one plane to the other. In otherwords, when the signal passes through a via that traverses this region,as in Figure 7.12 below , thesignal couples into the planar waveguide, as in Figure 7.13 below. SPICE doesn'tknow about this. Though this phenomenon can couple resonances to thesignal and cause signal problems, it also can usually be easilycontrolled.

Figure7.12. A Via Traversing a Planar Waveguide.
Figure7.13. Signal Injected into a Planar Waveguide

The cancellation of radiation by the presence of a complementarysignal, the other side of the differential pair, significantly reducesthe coupling to this waveguide. Radiation into this waveguide is asignificant factor in the total loss of a via, and, in the case of asingle-ended signal, is the major cause of signal loss. The way to dealwith vias is to calculate an appropriate L-C model through use of afield solver and import that model into SPICE.

When a planar waveguide has a lot of vias and holes in it, energyleaks out or is extracted fast enough that its probability of becomingresonant is low. However, if the waveguide has few holes and vias, itcan become resonant. This can cause a problem. The mechanism thatcouples your signal's energy into the waveguide also couples energy outof the waveguide.

The mechanism that converts part of your differential signal tocommon mode also converts common mode to differential energy. The endresult of this chain is that if you have a plane that goes resonant,you are likely to see that resonance in the differentialcharacteristics of the link.

This is yet another reason why you need to take care to minimizemode conversions by maintaining symmetry within your differential pair,as much as you can.

Plane-Splits
As with many other things examined above, SPICE does not know aboutplane splits, shown in Figure 7.14below. Signal integrity and the emissions impact will require adifferent tool if you are concerned. Emissions apply primarily to thecommon-mode component of a signal.

The signal-integrity impact can be modeled by treating the gap as api-network of capacitors. But the value of the capacitors is foundthrough use of a field solver. This is not too severe a problem if thisrule is followed: never cross a plane-split with any high-speed signal.

Figure7.14. A Signal Crossing a Plane Split

On the other hand, the impact of a narrow, say 10-mil wide gap, onthe signal integrity of a differential signal is not going to be verysignificant. If the particular design is such that emissions is not abig concern, crossing plane splits is not too big a concern either.

One approach that can be used is to assign some penalty to crossinga plane-split and use that as a criterion to help minimize the numberof plane-split crossings. That is, tell the architects and the layoutguys that each plane split is equivalent to reducing the overall usefultrace length by an inch. With features such as plane splits and vias,it is very hard to predict the precise impact.

They will increase loss, crosstalk, and emissions—but how much?Assigning an overall equivalent impact, such as claiming an overallusable distance reduction of an inch per, helps clarify the need tominimize such features in a high-speed pair. In some designs, thismight be overstating the fact. In others it might not.

Vias
A via has two main impacts at high frequencies: it can cause signalloss through injection to the planar waveguide and it can act as aresonant stub at microwave frequencies. The coupling to the planarwaveguide is linearly proportional to frequency; that is why thisphenomenon may not have been noticed by those working in the lower fewhundreds of megahertz.

As frequency increases, it becomes a much more serious issue. Again,a major advantage of differential signaling is that differential energyis far less impacted by this than is common-mode. When a differentialsignal traverses a planar waveguide through symmetrical andclosely-spaced vias, it is almost exclusively the common-mode componentthat loses energy to the waveguide.

A good side to this is if a single-ended signal has to traverse thewaveguide, and if the two planes are at the same potential, insert asecond via near the signal, using it to short the two planes together.

Image current will flow through the shorting via and largely cancelthe fields of the signal via. Losses will decrease. Surprisingly, thisworks even with differential signals. Adding a shorting via willdecrease loss in the signal vias.

A fairly good model of a via can be constructed by R-L-C componentswhere there is capacitor for each surface and reference plane, and aninductor for each region between. Such models can even be constructedwith reasonable accuracy through use of lookup tables.

Of course, the entries in the lookup table are calculated with afield solver. Such a model may not show the impact of shorting vias, ortheir absence, but it can show the impact of resonant stubs in the via.

Electrostatic Discharge
It has already been pointed out that SPICE knows nothing aboutelectromagnetic radiation. Neither does it know anything aboutelectrostatic discharge (ESD). ESD typically involves non-linearphenomena and, though they can be modeled, they are seldom included inmodels designed for signal integrity applications.

There is a very high significance for signal integrity in one aspectof ESD. Pins that are designed to withstand ESD typically do so throughthe use of current shunting devices, often diodes. These componentstypically add significant capacitance to the protected pin. Thatcapacitance shows up in circuit models as a value in parallel with thetermination resistor.

This capacitance is often the biggest problem preventing really goodvalues of return loss in microwave frequency ports. In typical systems,the better the ESD protection, the more capacitance. Because of this,very high speed ports often have very poor ESD protection. You need tokeep this in mind whenever you handle these devices.

Next  in Part 3:  Modelable Featuresof high performance designs
To read Part 1, go to “Unmodelable featuresof high performance designs

Dennis Miller has worked in electronics since 1963. His earlyengineering interests and education centered on control theory andnumerical analysis. Now his interests are signal integrity andnumerical analysis. Since joining IntelCorp. in 1991, he has been instrumental in the development ofInfiniband technology and similar high speed signaling technologies.

This series of articles is based on material from Designing HighSpeed Interconnect Circuits,” by Dennis Miller, used here with thepermission of Intel Press which holds all copyrights. It can bepurchased on-line.

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