A lot of embedded systems activity this week. First, the January/February ESD Magazine content is on line at Embedded.com, including:
Power Management 101 by Jack Ganssle
Demystitying constructors by Dan Saks
Using SystemC to build an SoC platform by TI’s James Aldis
CoreMark: A realistic way to benchmark CPUs by Markus Levy
To complement the useful information you will get from the SystemC article I recommend that you read two online contributions on high-level SoC systems design techniques, including:
Embedded System Level design, anyone?
Using the System Verilog configurable coverage model
I’ve included a Multicore Design Focus section with articles onvirtual design platforms for multicore design, multiprocessor offloadingin Ethernet switches, multicore coverage grading and multicore-basedauto body electronics.
In addition to breaking stories on ARM’sgraphics IP, ARM’s2011 CPU plans, Ceva’s cell phone DSP and Sony’s four-core ARM-based game console, there is news on some powerful new embedded software products: the Cantata++6.0 unit testing tools, Cobham’s Opera electromagnetic simulation tool and Artisian’sSysML Parasolver.
(Good reading!!– Embedded.com Editor Bernard Cole, , 928-525-9087)
Using SystemC to build a system-on-chip platform
How Texas Instruments' designers used the SystemC hardware design language to do performance modeling when creating both the company's OMAP-2 platform and the devices based on it.
CoreMark: A realistic way to benchmark CPU performance
The CoreMark CPU benchmark maximizes simplicity and efficacy.
Designing very high-order FIR filters with zero-stuffing
Richard Lyons, author of “Understanding digital signal processing,” describes a slick way around a high-order FIR filter design problem using a frequency -domain zero stuffing techÂ¬nique.
System Verilog configurable coverage model in OVM
OVM has brought in the concept of reusability of environment/agent across projects. But, a separate coverage model tends to be written for every project, compromising reusability. This paper presents the user with one possible solution – configurable and reusable coverage model, sighting AMBA AXI protocol as the case study for discussion.
To assess where Electronic System Level (ESL) is today, Chad Spackman, verification technologist at Open-Silicon, looks at the past progression of design entry methods and the fundamental motivations behind the progressions.
7 myths of analog and mixed-signal ASIC design Frostholm aims to help readers select the best partner for their analog and mixed-signal ASIC design.
USB simplified – adding USB to apps with legacy serial connections
USB-based microcontrollers may not offer the right peripheral set required for an application. A relatively painless and economical fix is to use fixed-function USB bridge chips to add USB connectivity to any embedded MCU-based system that uses serial communications.
Design Focus: Multicore SoC
Achieving first day multicore SoC software success
A well designed virtual platform is an integrated ecosystem that makes it easy to create or download models that allow design teams to combine them in ways that can initially be run fast and then switched to fullaccuracy to make precise measurements or to investigate low-level performance issues.
Tips and Trends: Processor Offload in the Switch
In many system designs, packets travel through an Ethernetswitch before reaching the NPU. Wouldn't it be ideal if the switch couldperform pre-processing for the NPU, eliminating the need for additional devicessuch as FPGAs? Read on.
Managing coverage grading in complex multicore microprocessors
Verification of a multicore design is substantially more complex than a single core design involving regressions that take a week or more. This article describes a customized coverage grading solution, co-developed by AMD and Synopsys, which has saved AMD several months of run time by providing an alternative grading methodology.
Multicore architectures for automotive body electronics
The increasing use of electronics in automobiles faces hurdles as the continuing need for more performance confronts the reality of the powerrequired to achieve that performance.
Cantata++ 6.0 provides cost-effective intelligent unit and integration testing
IT services company IPL has launched Cantata++ 6.0, the latest unit and integration testing software for C and C++ embedded systems developers. Cantata++ 6.0 is built on the Eclipse 3.5.2 open standard architecture with the highest level of integration with the Eclipse Workbench. It is easily deployed and greatly simplifies the configuration of unit testing on target platforms, providing a complete test development environment for the creation, execution and analysis of unit and integration tests for C and C++.
Version 14 of Opera electromagnetic simulation software delivers more speed and precision
Version 14 of Cobham's Opera electromagnetic design software greatly improves the speed and accuracy of simulation by extending the flexibility of finite element analysis meshing. The new version includes numerous other enhancements, including an integrated graphical circuit editor for defining associated electrical circuitry such as motor drive components.
Artisan Studio ParaSolver speeds exploration of complex SysML systems design alternatives
Atego has launched Artisan Studio ParaSolver, an add-on module for its Artisan Studio, the company's standards-based, model-driven development tool suite. Artisan Studio ParaSolver speeds up the process of exploring complex SysML design alternatives through the execution of SysML parametric models, enabling optimal system design solutions to be determined quickly and easily.
Cypress's new single-chip TrueTouch for tablets sports 60 sensing I/O channels
Cypress Semiconductor Corp. is offering a new, high-performance single-chip TrueTouch solution for large multitouch touchscreens up to 11.6 inches. The CY8CTMA884 family offers 60 sensing I/O channels with support for up to 884 nodes on the screen, more than any other single-chip solution, according to the company.
ARM plays catch-up in graphics IP
Despite all the jockeying, graphics IP still looks like a one-horse race, and ARM is trailing.
ARM updates roadmap with Kingfisher, Cygnet
Processor IP licensor ARM Holdings plc has tipped several additional cores in its roadmap for 2011 during a presentation provided as a background to the company's fourth quarter and full year financial results.
Four-core ARM A9 to run Sony game console
Sony Computer Entertainment has announced its next-generation portable (NGP) entertainment system will be run on a four-core Cortex-A9processor and a PowerVR SGX543MP4+ graphics core and will make its debutat the end of 2011.
Ceva claims top spot for cell phone DSP
DSP intellectual property supplier Ceva Inc. has claimed that is now the world's leading DSP architecture deployed in cellular baseband processors.
Enea and AppliedMicro expand multicore cooperation
Enea and AppliedMicro Inc. have formalized and expanded a longstandingalliance to focus on delivering advanced multicore hardware and softwaresolutions to the communications market.