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David Pellerin and Brian Durwood, Impulse Accelerated Technologies

Developing processor-compatible C-code for FPGA hardware acceleration

R.C. Cofer and Ben Harding

Basics of core-based FPGA design: Part 1 – core types & trade-offs

Highlights

What's all this cell phone stuff, anyway?

Hot Chips: the puzzle of many cores

Bits from Hot Chips: Robots, Cisco, Oracle

Hot Chips roundup

Editor's Note

Bernard Cole Site Editor Embedded.com

A must-read this week for many embedded systems designers is Ron Wilson's article on “The puzzle of many cores.” In it he surveys the action at this year's Hot Chips Conference and has noted a trend away from relatively “simple” three and four core multiprocessor chip designs to configurations in the 10s, 20s and even 100s and he delves into the impact this will have on software development.

To get a better sense of what challenges embedded systems developers will be facing in the future as a result of these new hardware designs, I recommend reading the following reports on developments at Hot Chips:

ARM wrestles with silicon, battery hurdles
Tensilica DSP core does 100 GMACs at 1W
IBM plants transactional memory in CPU
Bits from Hot Chips: robots, Cisco, Oracle
Hot Chips probes latest microprocessors

These reports make it clear that embedded developers have significant challenges ahead. This means you have a lot of homework to do. In addition to Embedded.com and ESD Magazine , resources you can depend on are the Embedded Systems Conferences and the classes they offer. At the 2011 Fall ESC in Boston, Sept. 26-28 , for example, class tracks that should be helpful include:

Multicore Development
System integration and test
Networking and connectivity
Microcontrollers and SoCs
Prototyping Embedded Systems

However, if you want to distract yourself from the tough issues that Hot Chips reveals, be sure to read Jack Ganssle's tongue-in-cheek comments on all things mobile in : “What's all this cell phone stuff, anyway? “

Design How Tos

Hot Chips: the puzzle of many cores

Papers at Hot Chips 2011 suggest that emphasis is shifting from multicore to manycore.

Hot Chips roundup

A roundup of stories from this years symposium.

Developing processor-compatible C-code for FPGA hardware acceleration

This article describes an iterative process for converting C code to run on FPGAs with or without processor cores, how to identify which code sections can best benefit from hardware acceleration, and coding styles to use to retain commonality.

Basics of core-based FPGA design: Part 1 – core types & trade-offs

In Part 1 in this four part series, the authors of “Rapid System Prototyping with FPGAs,” provide an overview of FPGA processor core types – firm, hard and soft – and the pros and cons that need to be evaluated in the context of an embedded system's requirements.

Understanding Smart Meters to Design Intelligent, Secure Systems

Keeping data secure is one of the major challenges facing both the utility companies and the e-meter vendors.

MILS architecture simplifies design of high assurance systems – Part 1

The Multiple independent levels of security (MILS) architecture provides a framework for development and validation of secure operating systems for military and avionics applications.

Predicting thermal runaway – Part 1

Preventing thermal runaway requires balancing power dissipated by the device with power dissipated by the system.

Heat Removal with Microchannel Heat Sinks

Liquid-cooled microchannel heat sinks and coolers can be an effective way to remove high heat load from both chips and boards.

Implementing advanced control strategies for DC/DC converters using MCUs (Part 1 of 2)

Sub: Understand how a microcontroller can provide superior performance for phase-shifted, full-bridge DC/DC converters

Making embedded processing development easy – part 3

Steven Magee, software architect, embedded processing, Texas Instruments provides the answer to the question: ” I really would like to protect my software investment and re-use my code. What's the best way to do this?”

Data security in cloud computing – Part 4: Cloud data storage

Part 4 of an excerpt from the book “Securing the Cloud: Cloud Computer Security Techniques and Tactics” looks at the benefits of cloud-based data storage and concerns over cloud “lock-in.”

Integrate USB into image sensing applications

Integrating USB to existing image sensor design may immensely increase the value to the flourishing image sensor market segment. The addition of USB will increase device functionality while providing an additional method to control and upgrade devices in the field.

Embedded Systems Bookshelf

Excerpts

Embedded Books Reading Room
Bernard Cole's favorite links to book excerpts.

Reviews

Engineer's Bookshelf
Airport fiction blows. A look at books other engineers are reading and why you should read them, too. Recommend and write a review yourself. E-mail Brian Fuller.

Jack Ganssle's Bookshelf
A list of book reviews by Jack Ganssle, contributing technical editor of Embedded Systems Design and Embedded.com.

Max's Cool Beans
Clive “Max” Maxfield, the editor on Programmable Logic DesignLine, often writes about interesting books.

Product News

PLS offers optimized dev tools for Infineon's new TC1791, TC1793 and TC1798 AUDO MAX 32-bit MCUs

Programmierbare Logik & Systeme's (PLS) Universal Debug Engine (UDE) 3.0.10, Universal Access Device (UAD2) family, and Universal Emulation Configurator (UEC) now support Infineon's AUDO MAX TC1791, TC1793 and TC1798 32-bit automotive microcontrollers (MCUs).

Wind River's Linux 4 Update Pack 2 adds rich graphics

Wind River Linux 4, Update Pack 2 is the first commercial embedded Linux to provide a fully integrated graphics software stack, from the board to the user interface framework level, for the latest Intel and Texas Instruments processors.

ST's new digital gyroscope has superior sensor resolution and audio/mechanical noise immunity

The L3GD20 three-axis digital-output gyroscope from STMicroelectronics combines high sensing resolution with outstanding immunity to audio noise and vibrations.

Samsung samples 30nm, 32GB DDR3 RDIMMs

In an effort to deliver higher performance with lower power consumption to the next-generation server market, Samsung has developed 32GB DDR3 RDIMMs that use 3D through silicon via (TSV) package technology.

Wind River Test Management 4.0 enables test coverage at the branch and block level

In version 4.0 of Wind River's Test Management, dynamic instrumentation technology enables test coverage at the branch and block level, working directly on optimized production binaries.

TI's dual 16-, 14- and 12-bit DACs provide highest precision, lowest power consumption

Texas Instruments Incorporated (TI) has announced that their family of dual 16-, 14- and 12-bit digital-to-analog converters (DACs) provide the industry's highest precision and lowest power consumption.

World's first dual channel brushless DC motor controller targets small electric vehicles and robotics

The HBL2350 from Roboteq, Inc is a dual channel, high current brushless motor controller, capable of simultaneously driving two brushless DC motors up to 75Amps each at up to 50V.

GE HD daq8580 video streaming appliance is optimized for unmanned vehicles

GE Intelligent Platforms has announced the daq8580 rugged streaming network appliance, a complete, standalone, application-ready solution that, according to the company, delivers flexibility, high performance and excellent cost-effectiveness.

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