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Paul Anderson, GrammaTech, Inc.

Static analysis vs. dynamic testing – No competition!

Sanjay Bhal and Stephen Lau

Overcoming the challenges of multicore software development

Issue Highlights

15 bugs away from being ready

Think static analysis cures all ills? Think again.

Editor's Note

Here is what's new on Embedded.com this week. While the immediate impacts of Japan’s triple whammy of earthquakes, tsunamis and nuclear plant problems are starting to settle, the secondary and tertiary effects of Japan’s disasters are making themselves felt throughout the world.

At first these events made me question the assumptions we make about the stability of the high tech society in which we are living. But on the positive side, these catastrophes made clear how our technology has  interlinked individuals and corporations in a way that forces us to cooperate and resolve our differences. What affects one country or group of people affects us all: financially, professionally and personally.

As the embedded systems design community worldwide adjusts to the rippling economic and business effects of the devastation, many of you are adjusting the same way you did when the current worldwide economic downturn hit: by keeping your focus on the future – the next new technology, standard, product, and agreement to enhance this connectivity. Some of the design articles, columns, products and news features that illuminate this future focus are: Web TV specs, solid-state lighting , optimized cellular M2M, multi-core software challenges and learning from our software bugs.

For stability’s sake, keep your focus on the future and the balance that brings to your life, but don’t forget to also think about how you can contribute – personally and professionally – to helping the Japanese deal with the devastation and regain their balance and stability. We are not only close neighbors in this ever-shrinking world, we are partners in the global high tech business.

—Bernard Cole
Site Editor, Embedded.com

(928) 525-9087

Design How Tos

Using simulation and emulation together to create complex SoCs

Laurent Ducousso, the IP verification manager for ST's HEG, uses EVE's ZeBu emulation platform to verify designs and delivers his observations.

Analog IP for multimedia SoCs: an eye on a world of essential analog features

Understand how analog IP meshes with the requirements of multimedia system-on-chip ICs

Optimizing cellular M2M apps for range and longevity

Embedded cellular modules for machine-to-machine applications should be designed from the ground up to meet M2M's rugged environmental requirements.

Practical implications of LTE on mobile baseband architecture implementations

The processing demand from LTE is enormous and so the very latest DSP and general-purpose processor architectures must be designed to take advantage of the semiconductor capability.

Time-domain simulations of high-speed links with X parameters

X parameters open the door for a large set of possibilities in the arenas of design, modeling and simulation. In addition to providing better techniques for predicting signal integrity performance in high-speed networks, they will generate many opportunities for research, development while providing a deeper insight into nonlinear modeling.

Understanding user interface design rules – Part 1: Task analysis and conceptual model

Part 1 of an excerpt from the book “Designing with the mind in mind: A simple guide to understanding user interface design rules” explains and demonstrates factors that affect how quickly people can learn to use interactive systems.

Double floating gate FET: potential unified memory device

A new device is invented based on a dual metal floating gate structure that can be employed as a unified memory, permitting combined dynamic and nonvolatile storage in the same device.

What makes an optimal SoC verification strategy

A typical SoC design for a consumer electronic device will have blocks that can be broadly classified into processors, DSP cores, peripherals, memory controllers, layered bus architectures and analog components. An optimal SoC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: ''what to verify', 'how to verify' and 'are we done'.

The real role of EDA in the Cloud

That great big storage bucket in the sky – the vast array of networked devices we call 'The Cloud' is a growing presence in our lives. Now EDA had to find its place in the Cloud.

ESC Silicon Valley 2011 Class Tracks

Architecture design
Best practices
Challenges & solutions in embedded designs
Connectivity and security
Debugging and optimizing
Design and test
DSP, communications & control design
HMI and multimedia
HW and platform design
Linux/Android/open source
Managing and process
MCUs in embedded designs
Memory in embedded systems
Multicore debug
Powering embedded designs
Programming for storage, I/O & networking
Programming languages and techniques
Programmable logic in embedded designs
Quality design & intellectual property
Reliability, security and performance
Remote monitoring and wireless networking
RTOS and real-time software
Safety design
Software Processes and Tools
Software Design
Systems architecture
Tools
Windows for embedded

Product News

Xelerated's HX336 NPU reduces power consumption by 50%, rapid transition to 100GE

The HX336 from Xelerated is a wirespeed single-chip network processor (NPU) with advanced traffic management and deep packet buffering for 100GE/OTU4 systems, the latest addition to Xelerated's HX family of network processors. The HX336 reduces power consumption by approximately 50 percent compared to competing multi-chip packet processing and traffic management solutions.

eDevice launches Cellgo, first low-current GSM/GPRS modem for M2M

Cellgo from eDevice is an external modem enabling serial devices to connect to the GSM/GPRS network through a single cable grouping both data and power signals. The internal Super Capacitor enables power-constrained products, such as battery-powered ones, to handle power bursts required during cellular data transmission.

ITTIA and Express Logic partner to offer ITTIA DB SQL for ThreadX

ITTIA DB SQL, a relational embedded database for special-purpose systems that require self-contained data management software, is now available for ThreadX, an advanced lightweight real-time operating system (RTOS) from Express Logic, Inc.

Dual core processor ready for space applications

Aeroflex Gaisler AB (Gothenburg, Sweden) has developed the GR712RC the fault tolerant processor, an implementation of a dual-core LEON3FT SPARC V8 processor using RadSafe technology.

Coin cell supercapacitors provide memory backup for critical circuits

The DC series of coin cell style supercapacitors from Illinois Capacitor provide on-board memory backup at much longer life spans than batteries.

8-bit MCUs include self-write flash program memory

Microchip Technology Inc. has expanded its 28-/40-pin PIC16F72X microcontroller (MCU) family with two additional 20-pin devices—the PIC16F(LF)720 and PIC16F(LF)721.