The proliferation of digital media into everyday electronics has changed the way consumers access and enjoy their media entertainment. Consumers today have the ability to listen to their entire music collection, watch movies, and browse photos all on a device no larger than a deck of playing cards. These advancements in technology however, are not without their challenges.
One such challenge is the task of transferring the digital media onto the device itself. The ubiquity of USB on PCs and portable devices has made USB the natural choice as the default method of media transfer. The ease with which USB allows users to transfer media, sync data, and charge their devices has only strengthened its position as a connection standard on mobile phones.
Many first generation devices, however, only supported Full-Speed USB, which allows for data rates up to 12Mb/s. With Full-Speed USB, 100 MP3s could painstakingly take upwards of an hour to transfer to a device. Wait times of this magnitude were unacceptable for consumers, who demanded something faster.
With media capabilities of phones expanding from just music to movies and beyond, the need for a faster transfer connection is growing as both data and storage sizes grows. The industry responded with Hi-Speed USB, offering a theoretical maximum transfer rate of 480Mb/s ” 40 times faster than that of Full-Speed USB.
Architecture Options for Hi-Speed USB
With Hi-Speed USB being an essential requirement for new media-centric electronics devices, designers have the choice of a few different architectures for supporting Hi-Speed USB (Figure 1 below ).
|Figure 1: Architectural Options for Hi-Speed USB|
The first option, if available, is to use the Hi-Speed USB logic within a chosen processor. In this configuration, Hi-Speed USB is supported directly by the processor, with an external USB transceiver used for the physical layer communication.
The USB transceiver is typically kept external to the processor for silicon area savings within the main processor, as the analog nature of a USB transceiver does not allow it to scale as well as digital when moving to smaller technologies such as 65nm and beyond. For this reason, it is often more cost and space effective to leave an analog component such as the USB transceiver external.
The second option is to use a standalone Hi-Speed USB controller. This device incorporates all of the blocks necessary to support Hi-Speed USB, including the SIE and transceiver. These devices typically connect to a host processor via a memory interface.
The third option is to use a bridge chip that can incorporate Hi-Speed USB support among other features, such as mass storage control. Similar to dedicated Hi-Speed USB controllers, these devices typically connect via the processor memory interface.
While Hi-Speed USB offers a theoretical max performance of 480 Mb/s, software overhead often prevents the theoretical max performance from being achieved in real world applications. The architecture and design of the Hi-Speed USB path, as a consequence, plays a vital role in determining the actual performance experienced.
For example, Table 1 below shows a sample of Hi-Speed USB-enabled phones, each with different Hi-Speed USB implementations, benchmarked for their USB performance. The usage scenario of a user transferring a video file of 677MB to mass storage on the phone was replicated on each phone under the same environment. For consistency, mass storage mode and the same removable mass storage was used in all cases.
|Table 1: Hi-Speed USB Benchmarks|
From the results, one can see that actual, real world Hi-Speed USB performance can vary immensely. The results range from transfer times of over 20 min (less than 10Mb/s) to under 1 min (over 140Mb/s), which is more than a factor of 25 difference. The answer to why there are such differences lies within the architecture of each method of USB support.
In the architecture where a standalone Hi-Speed USB controller is used, the controller typically connects to the processor via the main processor's external memory interface. This memory interface is also typically shared with memory devices such as NAND, which can be used for code or user data storage.
The incoming data from the host passes through the USB controller to the main processor. The processor at this point buffers the data into SDRAM before writing the data into mass storage. The entire process is a multi-step process which requires significant processor usage and limits USB transfer performance. The data flow in this scenario is illustrated in Figure 2 below .
|Figure 2: Standalone Hi-Speed USB Controller|
The next architectural option for Hi-Speed USB support is to use a processor which integrates the USB controller. Many of the processors which include Hi-Speed USB support also feature multiple CPU cores for enhanced processing capabilities, such as those required to support music and video playback. In this scenario, the ideal data path is shown in Figure 3 below .
|Figure 3: Integrated Hi-Speed USB Controller|
Since the USB controller is integrated within the processor, ideally the data is transferred directly from USB to the mass storage. However, the actual data path from USB to mass storage is not as straightforward as depicted. The actual data flow within the processor is shown in Figure 4 below .
|Figure 4: Actual Data Path From USB Controller to Mass Storage|
One of the CPU cores is used to control the USB SIE, while another CPU core is used for the mass storage controller. Each core shares the same SDRAM, which is partitioned into two memories dedicated to each CPU core.
As each CPU core does not have access to the other's memory, CPU1 must buffer the incoming data and then send the data to CPU2 where it is also buffered before writing to storage. This process can cause significant system load, which impacts overall USB performance.
The third architecture is to use a bridge chip architecture. Similar to the North and South bridge architecture in the PC industry, a bridge chip can provide support for peripherals not natively supported on processors. In the embedded world, a West Bridge architecture has been developed to address the need to quickly add support for new peripherals and communication protocols.
In this scenario, both the USB traffic and the mass storage are managed by the West Bridge controller. The data path for this architecture is shown in Figure 5 below .
|Figure 5: USB Utilizing West Bridge|
This architecture provides a direct path to the mass storage, thus optimizing the USB data path and performance to mass storage. Second, as the mass storage control and USB are supported by the bridge chip directly, the main baseband processor is offloaded of these tasks and freed for other tasks.
The independent data paths between the processor, storage, and PC allows for maximum efficiency when transferring data between any of the possible data paths. While this architecture offers the benefits discussed, it may come at the tradeoff of a higher system cost.
While it's clear that there is a range of Hi-Speed USB options available, the choice of architecture will ultimately depend on the desired features and specifications of the mobile device.
Simple devices with limited mass storage may suffice with USB integrated within the processor, while media centric devices with large amounts of storage require high performance sideloading capabilities. For the highest sideloading performance, a bridge chip offering a direct path to mass storage would be chosen.
With media and storage demands on mobile devices growing constantly, the need for high performance sideloading will only grow along with it. Along with this increased demand for high performance sideloading, mobile device designers must carefully examine what level of USB performance is right for their designs.
[Timothy Kung is a product manager in the Data Communications Division at Cypress Semiconductor. He has an BASc (Bachelors of Applied Science) from the University of Waterloo, in Waterloo, Canada. ]