Winbond cuts memory chip design time by 70 percent - Embedded.com

Winbond cuts memory chip design time by 70 percent

Winbond Electronics Corp.,(Taichung, Taiwan), is using  SpringSoft Inc.'s Laker Custom  Layout Automation System including the Laker digital routing solution to reduce by 70 percent the development time for memory chip designs targeting a variety of mobile memory applications, such as SDR, low power DDR, and cellular RAM.

The Laker system provides automated tools including routing solutions that enable Winbond design teams to achieve time savings at both the block and chip level, schematic-driven layout (SDL) flow to increase user productivity, and built-in scriptable cells that dramatically reduce cell library development time.

“Using Laker, our design teams have been able to drastically cut routing and verification cycles for 65-nanometer designs compared to other layout tools, while also continuously modifying designs to ensure the optimum power and highest quality implementation,” said Mu-Tsai Lo, deputy director of the DRAM Design Department III at Winbond.

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