Wireless MCU features dual-core architecture - Embedded.com

Wireless MCU features dual-core architecture

A pin-compatible derivative of ST’s STM32WB55 system-on-chip, the STM32WB50 Value Line wireless MCU supports Bluetooth 5.0, ZigBee 3.0, and OpenThread. The entry-level dual-core controller is based on an Arm Cortex-M4 core (application processor) running at 64 MHz and an Arm Cortex-M0+ core (network processor) running at 32 MHz.

The STM32WB50 targets a broad range of cost-sensitive industrial and consumer IoT applications, offering a good link budget from 100 dB in Bluetooth 5.0 mode up to 104 dB in IEEE 802.15.4 mode. With one core handling user application software and the other core running the radio subsystem, including the radio stack and security, the microcontroller is a good fit for developers seeking radio and application isolation for security reasons or real-time application constraints.

An AES-256 encryption engine and other basic security features are onboard, along with 1 Mbyte of flash and 128 kbytes of RAM. The dual-core architecture of the STM32WB50 allows over-the-air (OTA) updates for the radio stack, while integrated balun circuitry saves BOM cost and simplifies PCB layout.

Housed in a QFN48 package, the STM32WB50 microcontroller is in production now and costs $1.89 each in volume.

>> This article was originally published on our sister site, EDN.


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