WITTENSTEIN high integrity systems announce a new RISC-V port for SAFERTOS, the safety critical real-time operating system available pre-certified to ISO 26262 ASIL D and IEC 61508 SIL 3. The new SAFERTOS port targets a RISC-V core on the RV32M1 VEGAboard. The RV32M1 incorporates a PULP RI5CY RISC-V core, a PULP Zero RISCY RISC-V core, an Arm Cortex-M4 core, and an Arm Cortex-M0+ core.
RISC-V is a free and open Instruction Set Architecture. Founded in 2015, the RISC-V Foundation comprises more than 250 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
SAFERTOS is a safety critical RTOS that has been independently certified by TÜV SÜD to IEC 61508 SIL3 and ISO 26262 ASIL D. SAFERTOS is used internationally wherever safety is paramount, in sectors including Medical, Automotive and Industrial. SAFERTOS is used across a variety of multicore designs, and there is a straightforward upgrade path from the FreeRTOS kernel, the incredibly popular real-time OS.