As multicore and manycore systems emerge whose complexity is daunting to embedded software developers, they have looked with envy at such standardization efforts such as IEEE’s IP-XACT standard that defines and describes electronic components for EDA hardware design.
Created initially by the SPIRIT consortium, IP-XACT defines and describes electronic components and their designs as a way to automate configuration and integration of the various EDA tools in an system on chip design.
This was done by creating a standardized XML data format to describe components from multiple vendors and do so in a vendor-neutral way that would allow exchange of component libraries between diverse electronic design automation tools.
Developers of embedded multicore and manycore processor applications – and the suppliers of the tools they use – need no longer wait for such capabilities to come to software development.
Drawing to some degree on what IP-XACT has done for hardware components, the Multicore Association www.multicore-association.org has created the Software-Hardware Interface for Multi-Many core (SHIM) working group which will have as its goal the definition of a common interface to abstract the hardware properties that matter to multicore tools (see Figure below .)
According to Markus Levy, Multicore Association president, the working group aims to deliver, by the end of the year, an initial standard using XML models, then turn attention to ironing out implementation issues for specific use cases.
He said that while the IEEE's IP-XACT standard is related to SHIM in some ways, their emphasis is much different. Where IP-XACT gives more details on connections between hardware blocks and is intended for use by hardware designers, he said, SHIM presents more details about latencies, cache types and sizes, and other details of interest for its target audience of software developers.
“Multicore and manycore system development often gets sidetracked because development tool vendors and runtime systems for these programs are challenged to support the virtually unlimited number of processor configurations,” said Levy. “ The primary goal of the SHIM working group is to define an architecture description standard useful for software design.”
A good case in point, he said, is the way in which it will simplify the management of the processor cores, the inter-core communication channels, the memory system (including hierarchy, topology, coherency, memory size, latency), the network-on-chip (NoC) and routing protocols, and hardware virtualization features.
“These are among the architectural features that SHIM will either directly or indirectly describe,” he said, “and the aim is to make it flexible enough to allow vendor-specific, non-standard architectural information for customized tools.”
He said the standard will also simplify communications between chip vendors and tool suppliers. The former, he said, can use these models to automatically report details of their chips in a standard way to operating systems and developer tools such as performance analysis programs, runtime libraries, and auto-parallelizing compilers.
While the XML models will be publicly available, vendor-specific chip details can remain confidential between a processor vendor and its software partners.
And while the XML models are intended to be descriptive for configuration purposes and not for use in simulations, said Levy, they can be used to provide rough performance estimates that might inform decisions about how software automatically configures itself.
SHIM aims to replace manual software configuration by engineers and existing proprietary formats that handle similar jobs.
“ I think SHIM will be a useful adjunct for many types of tools,” said Levy, “including performance estimation, system configuration, and hardware modeling. “Performance information is critical for most software development tools, including performance analysis tools, auto-parallelizing compilers, and other parallelizing tools.”
Moreover, operating systems, middleware, and other runtime libraries, he said, require basic architectural information for system configuration. Because the SHIM standard can be used with hardware modeling to support architecture exploration, an important goal of the SHIM effort is to align it with work underway in the Multicore Association’s Tools Infrastructure Working Group (TIWG).
Initial work on SHIM was started about a year ago as part of a government-funded project in Japan, headed by Masaki Gondo, a general manager at eSOL , who opened contact with MCA leading to the formation of the working group, which Gondo is chairing.
Other members of the working group include Cavium, CriticalBlue, eSOL, Freescale Semiconductor, Mentor Graphics, Nagoya University, Nokia Siemens Networks, PolyCore Software, Renesas Electronics, Texas Instruments, TOPS Systems, Vector Fabrics, Wind River, and Xilinx.
“Ultimately, I hope SHIM will promote highly-optimized tools that can provide efficient utilization of very complex SoCs and eliminate the need for users to work their way through 1000-page manuals to program all the device features,” said Levy.