Xilinx boosts RFSoC performance with digital-front-end hard IP for 5G radios - Embedded.com

Xilinx boosts RFSoC performance with digital-front-end hard IP for 5G radios

Xilinx has announced its Zynq RFSoC digital front end (DFE) device designed for 5G New Radio (NR) deployments. Building on the company’s Zynq UltraScale architecture, the Zynq RFSoC DFE extends the Xilinx RFSoC family with a hard IP implementation of the compute-intensive functions required to effectively support 5G NR as well as legacy 4G in emerging 5G radio units (RUs).  

For all its potential, 5G brings multiple challenges to 5G infrastructure developers. While designers of smartphones and other mobile devices can choose from a growing array of 5G chipsets, the varied requirements associated with 5G’s broad range of capabilities typically demands more specialized solutions.  

While 3GPP Release 15 laid the groundwork for 5G NR with its focus on enhanced Mobile Broadband (eMBB), Release 16 earlier this year expanded 5G into new types of communications services bult around Ultra-Reliable Low-Latency Communication (URLLC) and massive Machine Type Communication (mMTC). URLLC addresses the need for minimum response delay required for critical applications such as industrial automation, remote surgery and transportation, while mMTC supports large-scale, high density deployments of smart devices in applications such as smart cities and smart factories. Future 3GPP releases will continue to extend 5G with capabilities such as NR MIMO (multiple-input and multiple-output), dynamic spectrum sharing, URLLC enhancements, and others in Release 17 as well as extended support for specific application areas in Release 18.  

Using 5G capabilities such as network function virtualization (NFV) and network slicing, 5G solution providers can provision specialized networks capable of delivering the unique combination of services required for each application and customer. Yet, delivering on the promise of extensive flexibility of 5G networks depends on the availability of devices able to offer a suitable combination of performance and flexibility as well as power efficiency.  

“With the market needs around 5G evolving, integrated RF solutions need to be adaptable to address future standards,” said Liam Madden, executive vice president and general manager of Xilinx’ Wired and Wireless Group, in a statement. “Zynq RFSoC DFE provides the optimal balance between that adaptability and fixed function IP.” 

The Zynq RFSoC DFE embeds hard IP that implements core functionality required in 5G RU signal paths (Figure 1).  

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Figure 1. The Zynq RFSoC DFE hard IP supports a broad range of processing capabilities required for 5G NR as well as legacy 4G radios. (Source: Xilinx)

Because the hard IP DFE core uses a smaller footprint than the equivalent soft IP implementation in the earlier Zynq RFSoC Gen 3 device, the new device can support more DFE cores, both increasing DFE compute performance and decreasing power consumption compared to the earlier device. As a result, the Zynq RFSoC DFE can achieve a minimum of 2x DFE processing performance per watt compared to a fully utilized Zynq RFSoC Gen 3 device, according to Xilinx.  

At the same time, developers can modify the signal path, bypassing hard IP blocks or inserting their own functionality implemented in the logic fabric (Figure 2).  

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Figure 2. The Zynq RFSoC DFE functional architecture combines hard IP, logic fabric and processor subsystem. (Source: Xilinx)

Zynq RFSoC DFE design documentation and support is available to early access customers, with shipments expected during the first half of 2021. For more information, visit the Xilinx RFSoC DFE product page. Xilinx is also providing further information on the device as part of its 5G virtual event on November 18-19. 


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