Xilinx releases OTN SmartCORE IP - Embedded.com

Xilinx releases OTN SmartCORE IP

At ECOC 2013, Xilinx, Inc. announced new OTN SmartCORE IP for high capacity combined Ethernet and 100G OTN switching platforms and Packet-Optical Transport Systems (P-OTS). Xilinx's SmartCORE IP portfolio is a strategic deliverable in Xilinx's roadmap to deliver All Programmable solutions needed to create, differentiate and evolve intelligent 400G and Nx100G OTN solutions and OTN switching platforms with high availability, low latency, low jitter and high Quality of Service (QoS) requirements.

The new OTN SmartCORE IP blocks are optimized for 7 series devices and include a group of comprehensive and environmentally agnostic APIs – available to abstract all common and complex functions to aid seamless integration into customer software:

  • 100G 1 Stage Multiplexer/Demultiplexer SmartCORE IP– Ultra-compact traffic aggregator, supporting any combination of up to 80 channels of ODUj traffic muxed into or demuxed from a high order ODU4.
  • OIF compliant 100G SAR SmartCORE IP– 80 channel segmentation and reassembly core which packetizes ODUjs into packet flows. This enables ODU traffic to be switched through a packet switch fabric, facilitating Packet Optical Transport systems.
  • 100G ODUMon SmartCORE IP – A bi-directional IP block used to perform overhead insertion and extraction on up to 80 ODUj channels. Used in conjunction with the Xilinx 128ch OTN Overhead Processor, it enables PM Monitoring, TCM Monitoring and/or TCM Termination and Generation with consequent action insertion for up to 6 levels of TCM on each of the ODUj channels.

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